changed bsn_source to bsn_source_v2

applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd

@@ -73,11 +73,12 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_adc IS
   CONSTANT c_eth_clk_period      : TIME := 8 ns;  -- 125 MHz XO on UniBoard
   CONSTANT c_ext_clk_period      : TIME := 5 ns;
   CONSTANT c_bck_ref_clk_period  : TIME := 5 ns;
-  CONSTANT c_pps_period          : NATURAL := 1000;
 
   CONSTANT c_tb_clk_period       : TIME := 100 ps; -- use fast tb_clk to speed up M&C
 
   CONSTANT c_nof_block_per_sync  : NATURAL := 16; 
+  CONSTANT c_nof_clk_per_sync    : NATURAL := c_nof_block_per_sync*c_sdp_N_fft; 
+  CONSTANT c_pps_period          : NATURAL := c_nof_clk_per_sync;
    
   CONSTANT c_percentage          : REAL := 0.05;  -- percentage that actual value may differ from expected value
   CONSTANT c_lo_factor           : REAL := 1.0 - c_percentage;  -- lower boundary  
@@ -91,14 +92,14 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_adc IS
   CONSTANT c_wg_freq_offset       : REAL := 0.0/11.0; -- in freq_unit
   CONSTANT c_subband_sp_0         : REAL := 102.0;  -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz 
   CONSTANT c_wg_ampl_lsb          : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl;  -- amplitude in number of LSbit resolution steps
-  CONSTANT c_exp_wg_power_sp_0      : REAL := REAL(c_ampl_sp_0**2)/2.0 * REAL(c_sdp_N_fft*c_nof_block_per_sync);
+  CONSTANT c_exp_wg_power_sp_0    : REAL := REAL(c_ampl_sp_0**2)/2.0 * REAL(c_nof_clk_per_sync);
 
   -- ADUH
   CONSTANT c_mon_buffer_nof_samples : NATURAL := 512; --samples per stream 
   
   -- MM  
   CONSTANT c_mm_file_reg_ppsh             : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
-  CONSTANT c_mm_file_reg_bsn_source       : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE";
+  CONSTANT c_mm_file_reg_bsn_source_v2       : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE";
   CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
   CONSTANT c_mm_file_reg_diag_wg          : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
   CONSTANT c_mm_file_reg_aduh_mon         : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_ADUH_MONITOR";
@@ -177,6 +178,7 @@ BEGIN
     g_sim                    => c_sim,
     g_sim_unb_nr             => c_unb_nr,
     g_sim_node_nr            => c_node_nr,
+    g_bsn_nof_clk_per_sync   => c_nof_clk_per_sync,                
     g_scope_selected_subband => NATURAL(c_subband_sp_0)
   )
   PORT MAP (
@@ -236,10 +238,10 @@ BEGIN
     ----------------------------------------------------------------------------
     -- Enable BS
     ----------------------------------------------------------------------------
-    mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 3,                    0, tb_clk);
-    mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 2,                    0, tb_clk);  -- Init BSN = 0
-    mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 1, c_nof_block_per_sync, tb_clk);  -- nof_block_per_sync
-    mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 0,         16#00000003#, tb_clk);  -- Enable BS at PPS
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3,                    0, tb_clk);
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2,                    0, tb_clk);  -- Init BSN = 0
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1,   c_nof_clk_per_sync, tb_clk);  -- nof_block_per_sync
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0,         16#00000003#, tb_clk);  -- Enable BS at PPS
     
     ----------------------------------------------------------------------------
     -- Enable WG

applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd

@@ -80,11 +80,12 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_bf IS
   CONSTANT c_ext_clk_period      : TIME := 5 ns;
   CONSTANT c_bck_ref_clk_period  : TIME := 5 ns;
   CONSTANT c_sa_clk_period       : TIME := tech_pll_clk_644_period; -- 644MHz
-  CONSTANT c_pps_period          : NATURAL := 1000;
 
   CONSTANT c_tb_clk_period       : TIME := 100 ps; -- use fast tb_clk to speed up M&C
 
   CONSTANT c_nof_block_per_sync  : NATURAL := 16;
+  CONSTANT c_nof_clk_per_sync    : NATURAL := c_nof_block_per_sync*c_sdp_N_fft; 
+  CONSTANT c_pps_period          : NATURAL := c_nof_clk_per_sync;
   CONSTANT c_wpfb_sim            : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
    
   CONSTANT c_percentage          : REAL := 0.05;  -- percentage that actual value may differ from expected value
@@ -99,7 +100,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_bf IS
   CONSTANT c_wg_freq_offset       : REAL := 0.0/11.0; -- in freq_unit
   CONSTANT c_subband_sp_0         : REAL := 102.0;  -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz 
   CONSTANT c_wg_ampl_lsb          : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl;  -- amplitude in number of LSbit resolution steps
-  CONSTANT c_exp_wg_power_sp_0      : REAL := REAL(c_ampl_sp_0**2)/2.0 * REAL(c_sdp_N_fft*c_nof_block_per_sync);
+  CONSTANT c_exp_wg_power_sp_0    : REAL := REAL(c_ampl_sp_0**2)/2.0 * REAL(c_nof_clk_per_sync);
 
   -- WPFB
   CONSTANT c_wb_leakage_bin                 : NATURAL := c_wpfb_sim.nof_points / c_wpfb_sim.wb_factor;   -- = 256, leakage will occur in this bin if FIR wb_factor is reversed 
@@ -112,7 +113,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_bf IS
 
   -- MM  
   CONSTANT c_mm_file_reg_ppsh             : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
-  CONSTANT c_mm_file_reg_bsn_source       : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE";
+  CONSTANT c_mm_file_reg_bsn_source_v2       : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE";
   CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
   CONSTANT c_mm_file_reg_diag_wg          : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
   CONSTANT c_mm_file_ram_st_bst           : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_BST";
@@ -219,6 +220,7 @@ BEGIN
     g_sim_unb_nr             => c_unb_nr,
     g_sim_node_nr            => c_node_nr,
     g_wpfb                   => c_wpfb_sim,
+    g_bsn_nof_clk_per_sync   => c_nof_clk_per_sync,
     g_scope_selected_subband => NATURAL(c_subband_sp_0)
   )
   PORT MAP (
@@ -330,10 +332,10 @@ BEGIN
     ----------------------------------------------------------------------------
     -- Enable BS
     ----------------------------------------------------------------------------
-    mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 3,                    0, tb_clk);
-    mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 2,                    0, tb_clk);  -- Init BSN = 0
-    mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 1, c_nof_block_per_sync, tb_clk);  -- nof_block_per_sync
-    mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 0,         16#00000003#, tb_clk);  -- Enable BS at PPS
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3,                    0, tb_clk);
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2,                    0, tb_clk);  -- Init BSN = 0
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk);  -- nof_block_per_sync
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0,         16#00000003#, tb_clk);  -- Enable BS at PPS
     
     ----------------------------------------------------------------------------
     -- Enable WG

applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd

@@ -74,11 +74,12 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_fsub IS
   CONSTANT c_eth_clk_period      : TIME := 8 ns;  -- 125 MHz XO on UniBoard
   CONSTANT c_ext_clk_period      : TIME := 5 ns;
   CONSTANT c_bck_ref_clk_period  : TIME := 5 ns;
-  CONSTANT c_pps_period          : NATURAL := 1000;
 
   CONSTANT c_tb_clk_period       : TIME := 100 ps; -- use fast tb_clk to speed up M&C
 
   CONSTANT c_nof_block_per_sync  : NATURAL := 16;
+  CONSTANT c_nof_clk_per_sync    : NATURAL := c_nof_block_per_sync*c_sdp_N_fft; 
+  CONSTANT c_pps_period          : NATURAL := c_nof_clk_per_sync;
   CONSTANT c_wpfb_sim            : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
    
   CONSTANT c_percentage          : REAL := 0.05;  -- percentage that actual value may differ from expected value
@@ -93,7 +94,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_fsub IS
   CONSTANT c_wg_freq_offset       : REAL := 0.0/11.0; -- in freq_unit
   CONSTANT c_subband_sp_0         : REAL := 102.0;  -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz 
   CONSTANT c_wg_ampl_lsb          : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl;  -- amplitude in number of LSbit resolution steps
-  CONSTANT c_exp_wg_power_sp_0    : REAL := REAL(c_ampl_sp_0**2)/2.0 * REAL(c_sdp_N_fft*c_nof_block_per_sync);
+  CONSTANT c_exp_wg_power_sp_0    : REAL := REAL(c_ampl_sp_0**2)/2.0 * REAL(c_nof_clk_per_sync);
 
   -- WPFB
   CONSTANT c_nof_pfb                        : NATURAL := 1; -- Verifying 1 of c_sdp_P_pfb = 6 pfb to speed up simulation.
@@ -107,7 +108,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_fsub IS
 
   -- MM  
   CONSTANT c_mm_file_reg_ppsh             : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
-  CONSTANT c_mm_file_reg_bsn_source       : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE";
+  CONSTANT c_mm_file_reg_bsn_source_v2       : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE";
   CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
   CONSTANT c_mm_file_reg_diag_wg          : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
   CONSTANT c_mm_file_ram_st_sst           : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
@@ -192,6 +193,7 @@ BEGIN
     g_sim_unb_nr             => c_unb_nr,
     g_sim_node_nr            => c_node_nr,
     g_wpfb                   => c_wpfb_sim,
+    g_bsn_nof_clk_per_sync   => c_nof_clk_per_sync,
     g_scope_selected_subband => NATURAL(c_subband_sp_0)
   )
   PORT MAP (
@@ -250,10 +252,10 @@ BEGIN
     ----------------------------------------------------------------------------
     -- Enable BS
     ----------------------------------------------------------------------------
-    mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 3,                    0, tb_clk);
-    mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 2,                    0, tb_clk);  -- Init BSN = 0
-    mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 1, c_nof_block_per_sync, tb_clk);  -- nof_block_per_sync
-    mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 0,         16#00000003#, tb_clk);  -- Enable BS at PPS
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3,                    0, tb_clk);
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2,                    0, tb_clk);  -- Init BSN = 0
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1,   c_nof_clk_per_sync, tb_clk);  -- nof_block_per_sync
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0,         16#00000003#, tb_clk);  -- Enable BS at PPS
     
     ----------------------------------------------------------------------------
     -- Enable WG

applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd

@@ -56,6 +56,7 @@ ENTITY lofar2_unb2b_sdp_station IS
     g_factory_image          : BOOLEAN := FALSE;
     g_protect_addr_range     : BOOLEAN := FALSE;
     g_wpfb                   : t_wpfb := c_sdp_wpfb_subbands;
+    g_bsn_nof_clk_per_sync   : NATURAL := c_sdp_f_adc_MHz*10**6;  -- Default 200M, overide for short simulation 
     g_scope_selected_subband : NATURAL := 0
   );
   PORT (
@@ -670,7 +671,8 @@ BEGIN
   u_ait: ENTITY lofar2_sdp_lib.node_sdp_adc_input_and_timing
   GENERIC MAP(
     g_technology                => g_technology,
-    g_sim                       => g_sim                
+    g_sim                       => g_sim,
+    g_bsn_nof_clk_per_sync      => g_bsn_nof_clk_per_sync                
   )
   PORT MAP(
     -- clocks and resets

applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd

@@ -116,8 +116,6 @@ ARCHITECTURE str OF node_sdp_adc_input_and_timing IS
   -- Frame parameters TBC
   CONSTANT c_bs_bsn_w               : NATURAL := 64; --51;
   CONSTANT c_bs_block_size          : NATURAL := c_sdp_N_fft; -- =1024;
-  CONSTANT c_bs_nof_clk_per_sync    : NATURAL := 2 * c_sdp_f_adc_MHz * 10**6;  -- = 400M, use a sync interval of 2s for testing
-  CONSTANT c_bs_nof_block_per_sync  : NATURAL := c_bs_nof_clk_per_sync / c_sdp_N_fft; -- = 390625, to have integer number of blocks per sync interval for testing
   CONSTANT c_dp_fifo_dc_size        : NATURAL := 64;
  
   -- JESD signals
@@ -234,7 +232,7 @@ BEGIN
   -----------------------------------------------------------------------------
   -- Timestamp
   -----------------------------------------------------------------------------  
-  u_bsn_source : ENTITY dp_lib.mms_dp_bsn_source_v2
+  u_bsn_source_v2 : ENTITY dp_lib.mms_dp_bsn_source_v2
   GENERIC MAP (
     g_cross_clock_domain     => TRUE,
     g_block_size             => c_bs_block_size,
@@ -391,7 +389,7 @@ BEGIN
     g_nof_streams          => c_sdp_S_pn,
     g_symbol_w             => c_sdp_W_adc_jesd,  
     g_nof_symbols_per_data => 1,          -- Wideband factor is 1          
-    g_nof_accumulations    => c_bs_nof_clk_per_sync
+    g_nof_accumulations    => g_bsn_nof_clk_per_sync
   )
   PORT MAP (
     -- Memory-mapped clock domain