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Commit f9d04a3b authored by Eric Kooistra's avatar Eric Kooistra
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Only accept JESD204B IP reset when the processing is disabled.

parent 2ec856c5
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1 merge request!263Resolve L2SDP-755
Pipeline #32714 passed
...@@ -212,6 +212,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_adc_jesd IS ...@@ -212,6 +212,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_adc_jesd IS
-- Debug signals to track progress of p_stimuli in Wave Window -- Debug signals to track progress of p_stimuli in Wave Window
SIGNAL dbg_restart : NATURAL := 0; SIGNAL dbg_restart : NATURAL := 0;
SIGNAL dbg_bsn_source_en : STD_LOGIC := '0'; SIGNAL dbg_bsn_source_en : STD_LOGIC := '0';
SIGNAL dbg_jesd_ctrl_reset_ignore : STD_LOGIC := '0';
SIGNAL dbg_jesd_ctrl_reset : STD_LOGIC := '0'; SIGNAL dbg_jesd_ctrl_reset : STD_LOGIC := '0';
SIGNAL dbg_read_jesd204b : STD_LOGIC := '0'; SIGNAL dbg_read_jesd204b : STD_LOGIC := '0';
SIGNAL dbg_link_reinit : STD_LOGIC := '0'; SIGNAL dbg_link_reinit : STD_LOGIC := '0';
...@@ -592,6 +593,31 @@ BEGIN ...@@ -592,6 +593,31 @@ BEGIN
ASSERT v_sp_power_sum_0 > c_lo_factor * c_exp_wg_power_sp_0 REPORT "Wrong SP power for SP 0" SEVERITY ERROR; ASSERT v_sp_power_sum_0 > c_lo_factor * c_exp_wg_power_sp_0 REPORT "Wrong SP power for SP 0" SEVERITY ERROR;
ASSERT v_sp_power_sum_0 < c_hi_factor * c_exp_wg_power_sp_0 REPORT "Wrong SP power for SP 0" SEVERITY ERROR; ASSERT v_sp_power_sum_0 < c_hi_factor * c_exp_wg_power_sp_0 REPORT "Wrong SP power for SP 0" SEVERITY ERROR;
-- Try to reset via JESD_CTRL. This JESD_CTRL should be ignored.
-- Note: Awkward way to set MSbit without negative integer warning, using TO_SINT(v_word).
dbg_jesd_ctrl_reset_ignore <= '1'; -- marker in wave window
-- apply JESD_CTRL reset
v_word := (OTHERS => '0');
v_word(c_sdp_jesd_ctrl_reset_bi) := '1'; -- reset
mmf_mm_bus_wr(c_mm_file_pio_jesd_ctrl, 0, TO_SINT(v_word), tb_clk);
proc_common_wait_cross_clock_domain_latency(tb_clk, ext_clk);
mmf_mm_bus_rd(c_mm_file_pio_jesd_ctrl, 0, rd_data, tb_clk);
pio_jesd_ctrl <= rd_data;
pio_jesd_ctrl_enable <= rd_data(c_sdp_jesd_ctrl_enable_w-1 DOWNTO 0);
pio_jesd_ctrl_reset <= rd_data(c_sdp_jesd_ctrl_reset_bi);
proc_common_wait_some_cycles(tb_clk, 1);
ASSERT pio_jesd_ctrl_reset = '0' REPORT "JESD_CTRL reset should be ignored when BSN source is on." SEVERITY ERROR;
-- remove JESD_CTRL reset
v_word := (OTHERS => '0');
v_word(c_sdp_jesd_ctrl_reset_bi) := '0'; -- reset
mmf_mm_bus_wr(c_mm_file_pio_jesd_ctrl, 0, TO_SINT(v_word), tb_clk);
proc_common_wait_cross_clock_domain_latency(tb_clk, ext_clk);
mmf_mm_bus_rd(c_mm_file_pio_jesd_ctrl, 0, rd_data, tb_clk);
pio_jesd_ctrl <= rd_data;
pio_jesd_ctrl_enable <= rd_data(c_sdp_jesd_ctrl_enable_w-1 DOWNTO 0);
pio_jesd_ctrl_reset <= rd_data(c_sdp_jesd_ctrl_reset_bi);
dbg_jesd_ctrl_reset_ignore <= '0';
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Restart AIT -- Restart AIT
-- . JESD_CTRL reset stops JESD204B OUT rx_clk and asserts JESD204B OUT -- . JESD_CTRL reset stops JESD204B OUT rx_clk and asserts JESD204B OUT
...@@ -619,6 +645,8 @@ BEGIN ...@@ -619,6 +645,8 @@ BEGIN
pio_jesd_ctrl <= rd_data; pio_jesd_ctrl <= rd_data;
pio_jesd_ctrl_enable <= rd_data(c_sdp_jesd_ctrl_enable_w-1 DOWNTO 0); pio_jesd_ctrl_enable <= rd_data(c_sdp_jesd_ctrl_enable_w-1 DOWNTO 0);
pio_jesd_ctrl_reset <= rd_data(c_sdp_jesd_ctrl_reset_bi); pio_jesd_ctrl_reset <= rd_data(c_sdp_jesd_ctrl_reset_bi);
proc_common_wait_some_cycles(tb_clk, 1);
ASSERT pio_jesd_ctrl_reset = '1' REPORT "JESD_CTRL reset should be applied when BSN source is off." SEVERITY ERROR;
WAIT FOR 1 us; WAIT FOR 1 us;
-- Read Rx JESD_204B IP status during reset -- Read Rx JESD_204B IP status during reset
......
...@@ -141,8 +141,10 @@ ARCHITECTURE str OF node_sdp_adc_input_and_timing IS ...@@ -141,8 +141,10 @@ ARCHITECTURE str OF node_sdp_adc_input_and_timing IS
SIGNAL st_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); SIGNAL st_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL mm_rst_jesd : STD_LOGIC; SIGNAL mm_rst_jesd : STD_LOGIC;
SIGNAL mm_jesd_ctrl_reg : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); SIGNAL mm_jesd_ctrl_reg_wr : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL mm_jesd_ctrl_reg_rd : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL jesd204b_disable_arr : STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0); SIGNAL jesd204b_disable_arr : STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0);
SIGNAL jesd204b_reset_request : STD_LOGIC := '0';
BEGIN BEGIN
...@@ -161,10 +163,21 @@ BEGIN ...@@ -161,10 +163,21 @@ BEGIN
-- complete blocks, so from sop to eop. Therefore, first mms_dp_bsn_source_v2 should be -- complete blocks, so from sop to eop. Therefore, first mms_dp_bsn_source_v2 should be
-- disabled to stop and flush the block processing, before applying mm_rst_jesd. -- disabled to stop and flush the block processing, before applying mm_rst_jesd.
mm_rst_jesd <= mm_rst OR mm_jesd_ctrl_reg(c_sdp_jesd_ctrl_reset_bi); -- Only accept JESD204B IP reset when the processing is disabled (indicated by bs_sosi.valid
gen_jesd_disable : FOR I IN 0 TO c_sdp_S_pn-1 GENERATE -- = '0'), to avoid corrupt bs_sosi blocks entering the subsequent processing due to that a
jesd204b_disable_arr(i) <= mm_jesd_ctrl_reg(i); -- JESD204B IP reset causes that the rx_clk stops.
END GENERATE; mm_rst_jesd <= mm_rst OR jesd204b_reset_request;
jesd204b_disable_arr <= mm_jesd_ctrl_reg_wr(c_sdp_S_pn-1 DOWNTO 0);
jesd204b_reset_request <= mm_jesd_ctrl_reg_wr(c_sdp_jesd_ctrl_reset_bi) AND NOT bs_sosi.valid;
p_mm_jesd_ctrl_reg_rd : PROCESS(mm_jesd_ctrl_reg_wr, jesd204b_reset_request)
BEGIN
-- default readback what was written
mm_jesd_ctrl_reg_rd <= mm_jesd_ctrl_reg_wr;
-- report actual JESD204B reset status
mm_jesd_ctrl_reg_rd(c_sdp_jesd_ctrl_reset_bi) <= jesd204b_reset_request;
END PROCESS;
gen_jesd : IF g_no_jesd = FALSE GENERATE gen_jesd : IF g_no_jesd = FALSE GENERATE
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
...@@ -202,7 +215,6 @@ BEGIN ...@@ -202,7 +215,6 @@ BEGIN
serial_rx_arr => JESD204B_SERIAL_DATA(c_sdp_S_pn-1 downto 0) serial_rx_arr => JESD204B_SERIAL_DATA(c_sdp_S_pn-1 downto 0)
); );
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Time delay: dp_shiftram -- Time delay: dp_shiftram
-- . copied from unb1_bn_capture_input (apertif) -- . copied from unb1_bn_capture_input (apertif)
...@@ -221,7 +233,6 @@ BEGIN ...@@ -221,7 +233,6 @@ BEGIN
END LOOP; END LOOP;
END PROCESS; END PROCESS;
u_dp_shiftram : ENTITY dp_lib.dp_shiftram u_dp_shiftram : ENTITY dp_lib.dp_shiftram
GENERIC MAP ( GENERIC MAP (
g_nof_streams => c_sdp_S_pn, g_nof_streams => c_sdp_S_pn,
...@@ -528,8 +539,8 @@ BEGIN ...@@ -528,8 +539,8 @@ BEGIN
rd_dat => jesd_ctrl_miso.rddata(c_sdp_mm_jesd_ctrl_reg.dat_w-1 DOWNTO 0), rd_dat => jesd_ctrl_miso.rddata(c_sdp_mm_jesd_ctrl_reg.dat_w-1 DOWNTO 0),
rd_val => OPEN, rd_val => OPEN,
-- data side -- data side
out_reg => mm_jesd_ctrl_reg, out_reg => mm_jesd_ctrl_reg_wr,
in_reg => mm_jesd_ctrl_reg in_reg => mm_jesd_ctrl_reg_rd
); );
END str; END str;
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