corrected TB

libraries/io/eth/tb/vhdl/tb_eth_tester_high_bw.vhd

@@ -111,9 +111,7 @@ ARCHITECTURE tb OF tb_eth_tester_high_bw IS
   -- Expected Tx --> Rx latency values obtained from a tb run
   CONSTANT c_tx_exp_latency          : NATURAL := 0;
   CONSTANT c_rx_exp_latency_en       : BOOLEAN := c_bg_block_len_max >= 50;
-  CONSTANT c_rx_exp_latency_st       : NATURAL := 28;
-  CONSTANT c_rx_exp_latency_sim_tse  : NATURAL := 167;
-  CONSTANT c_rx_exp_latency_tech_tse : NATURAL := 372;
+  CONSTANT c_rx_exp_latency_st       : NATURAL := 19;
 
   -- CRC is added by Tx TSE IP and removed by dp_offload_rx when g_remove_crc =
   -- g_loopback_eth = TRUE. Therefore internally only application payload
@@ -267,6 +265,9 @@ BEGIN
     ---------------------------------------------------------------------------
     FOR I IN g_nof_streams-1 DOWNTO 0 LOOP
       v_offset := I * c_diag_bg_reg_adr_span;
+      -- Set number of octets per packet for dp_split
+      proc_mem_mm_bus_wr(I*2, bg_ctrl_arr(I).samples_per_packet, mm_clk, reg_dp_split_copi);
+
       -- Prepare the BG
       proc_mem_mm_bus_wr(v_offset + 1, ceil_div(bg_ctrl_arr(I).samples_per_packet, g_nof_octet_generate) , mm_clk, reg_bg_ctrl_copi);
       proc_mem_mm_bus_wr(v_offset + 2, bg_ctrl_arr(I).blocks_per_sync,    mm_clk, reg_bg_ctrl_copi);
@@ -277,9 +278,6 @@ BEGIN
       proc_mem_mm_bus_wr(v_offset + 7, 0,                                 mm_clk, reg_bg_ctrl_copi);  -- high part
       -- Enable the BG at st_pps pulse.
       proc_mem_mm_bus_wr(v_offset + 0, 3, mm_clk, reg_bg_ctrl_copi);
- 
-      -- Set number of octets per packet for dp_split
-      proc_mem_mm_bus_wr(I*2, bg_ctrl_arr(I).samples_per_packet, mm_clk, reg_dp_split_copi);
 
     END LOOP;
     proc_common_wait_some_cycles(mm_clk, 10);