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Commit f8e89843 authored by Reinier van der Walle's avatar Reinier van der Walle
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increased BSN monitor timeout for subband correlator.

parent 177f1d20
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1 merge request!264increased BSN monitor timeout for subband correlator.
Pipeline #32787 failed
...@@ -325,7 +325,7 @@ BEGIN ...@@ -325,7 +325,7 @@ BEGIN
g_use_mm_output => TRUE, g_use_mm_output => TRUE,
g_rd_latency => 1, -- Required for st_xst g_rd_latency => 1, -- Required for st_xst
-- for mms_dp_bsn_monitor_v2 -- for mms_dp_bsn_monitor_v2
g_nof_clk_per_sync => c_sdp_N_clk_sync_timeout, -- Using c_sdp_N_clk_sync_timeout as g_nof_clk_per_sync is used for BSN monitor timeout. g_nof_clk_per_sync => c_sdp_N_clk_sync_timeout_xsub, -- Using c_sdp_N_clk_sync_timeout_xsub as g_nof_clk_per_sync is used for BSN monitor timeout.
g_nof_input_bsn_monitors => g_P_sq, g_nof_input_bsn_monitors => g_P_sq,
g_use_bsn_output_monitor => TRUE g_use_bsn_output_monitor => TRUE
) )
...@@ -439,7 +439,8 @@ BEGIN ...@@ -439,7 +439,8 @@ BEGIN
g_statistics_type => "XST", g_statistics_type => "XST",
g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time), g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time),
g_P_sq => g_P_sq, g_P_sq => g_P_sq,
g_crosslets_direction => 1 -- = lane direction g_crosslets_direction => 1, -- = lane direction
g_bsn_monitor_sync_timeout => c_sdp_N_clk_sync_timeout_xsub
) )
PORT MAP ( PORT MAP (
mm_clk => mm_clk, mm_clk => mm_clk,
......
...@@ -114,6 +114,7 @@ PACKAGE sdp_pkg is ...@@ -114,6 +114,7 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus CONSTANT c_sdp_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
CONSTANT c_sdp_N_clk_per_sync : NATURAL := c_sdp_f_adc_MHz*10**6; -- Default 200M clock cycles per second CONSTANT c_sdp_N_clk_per_sync : NATURAL := c_sdp_f_adc_MHz*10**6; -- Default 200M clock cycles per second
CONSTANT c_sdp_N_clk_sync_timeout : NATURAL := c_sdp_f_adc_MHz*10**6 + c_sdp_f_adc_MHz*10**5; -- 10% margin. CONSTANT c_sdp_N_clk_sync_timeout : NATURAL := c_sdp_f_adc_MHz*10**6 + c_sdp_f_adc_MHz*10**5; -- 10% margin.
CONSTANT c_sdp_N_clk_sync_timeout_xsub : NATURAL := 2**31 - 1; -- 10.7 seconds = largest value for NATURAL.
CONSTANT c_sdp_N_sync_jesd : NATURAL := c_sdp_S_pn * c_sdp_N_sync_rcu / c_sdp_S_rcu; -- = 4, nof JESD IP sync outputs per PN CONSTANT c_sdp_N_sync_jesd : NATURAL := c_sdp_S_pn * c_sdp_N_sync_rcu / c_sdp_S_rcu; -- = 4, nof JESD IP sync outputs per PN
CONSTANT c_sdp_f_sub_Hz : REAL := REAL(c_sdp_f_adc_MHz * 10**6) / REAL(c_sdp_N_fft); CONSTANT c_sdp_f_sub_Hz : REAL := REAL(c_sdp_f_adc_MHz * 10**6) / REAL(c_sdp_N_fft);
CONSTANT c_sdp_N_int : NATURAL := c_sdp_f_adc_MHz * 10**6; -- nof ADC sample periods per 1 s integration interval CONSTANT c_sdp_N_int : NATURAL := c_sdp_f_adc_MHz * 10**6; -- nof ADC sample periods per 1 s integration interval
......
...@@ -114,7 +114,8 @@ ENTITY sdp_statistics_offload IS ...@@ -114,7 +114,8 @@ ENTITY sdp_statistics_offload IS
g_beamset_id : NATURAL := 0; g_beamset_id : NATURAL := 0;
g_P_sq : NATURAL := c_sdp_P_sq; -- number of available correlator cells, g_P_sq : NATURAL := c_sdp_P_sq; -- number of available correlator cells,
g_crosslets_direction : NATURAL := 1; -- > 0 for crosslet transport in positive direction (incrementing RN), else 0 for negative direction g_crosslets_direction : NATURAL := 1; -- > 0 for crosslet transport in positive direction (incrementing RN), else 0 for negative direction
g_reverse_word_order : BOOLEAN := TRUE -- default word order is MSB after LSB, we need to stream LSB after MSB. g_reverse_word_order : BOOLEAN := TRUE; -- default word order is MSB after LSB, we need to stream LSB after MSB.
g_bsn_monitor_sync_timeout : NATURAL := c_sdp_N_clk_sync_timeout
); );
PORT ( PORT (
-- Clocks and reset -- Clocks and reset
...@@ -575,7 +576,7 @@ BEGIN ...@@ -575,7 +576,7 @@ BEGIN
GENERIC MAP ( GENERIC MAP (
g_nof_streams => 1, g_nof_streams => 1,
g_cross_clock_domain => TRUE, g_cross_clock_domain => TRUE,
g_sync_timeout => c_sdp_N_clk_sync_timeout, g_sync_timeout => g_bsn_monitor_sync_timeout,
g_bsn_w => c_dp_stream_bsn_w, g_bsn_w => c_dp_stream_bsn_w,
g_error_bi => 0, g_error_bi => 0,
g_cnt_sop_w => c_word_w, g_cnt_sop_w => c_word_w,
......
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