corrected address width

libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd

@@ -61,7 +61,7 @@ END mms_dp_bsn_monitor_v2;
 
 ARCHITECTURE str OF mms_dp_bsn_monitor_v2 IS
 
-  CONSTANT c_reg_adr_w : NATURAL := ceil_log2(9);
+  CONSTANT c_reg_adr_w : NATURAL := ceil_log2(7);
 
   SIGNAL mon_evt_arr           : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
   SIGNAL mon_sync_timeout_arr  : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);