Skip to content
Snippets Groups Projects
Commit f74209be authored by Reinier van der Walle's avatar Reinier van der Walle
Browse files

WIP: fixed latches

parent 8a9f147b
Branches
No related tags found
1 merge request!114Resolve L2SDP-296
...@@ -167,6 +167,7 @@ BEGIN ...@@ -167,6 +167,7 @@ BEGIN
BEGIN BEGIN
v := r; v := r;
v.col_select_mosi := c_mem_mosi_rst; v.col_select_mosi := c_mem_mosi_rst;
v_offsets := r.offsets;
-- start/restart -- start/restart
IF start_trigger = '1' THEN IF start_trigger = '1' THEN
......
...@@ -62,17 +62,17 @@ ARCHITECTURE rtl OF st_xsq_mm_to_dp IS ...@@ -62,17 +62,17 @@ ARCHITECTURE rtl OF st_xsq_mm_to_dp IS
crosslets_index : NATURAL; crosslets_index : NATURAL;
in_a_index : NATURAL; in_a_index : NATURAL;
in_b_index : NATURAL; in_b_index : NATURAL;
mm_mosi : t_mem_mosi;
END RECORD; END RECORD;
CONSTANT c_reg_rst : t_reg := (c_dp_sosi_rst, c_dp_sosi_rst, '0', 0, 0, 0); CONSTANT c_reg_rst : t_reg := (c_dp_sosi_rst, c_dp_sosi_rst, '0', 0, 0, 0, c_mem_mosi_rst);
SIGNAL r : t_reg; SIGNAL r : t_reg;
SIGNAL nxt_r : t_reg; SIGNAL nxt_r : t_reg;
SIGNAL mm_mosi : t_mem_mosi := c_mem_mosi_rst;
BEGIN BEGIN
mm_mosi_arr <= (OTHERS => mm_mosi); -- all mosi are identical. mm_mosi_arr <= (OTHERS => nxt_r.mm_mosi); -- all mosi are identical.
u_sosi : PROCESS(r, mm_miso_arr) u_sosi : PROCESS(r, mm_miso_arr)
BEGIN BEGIN
...@@ -98,7 +98,7 @@ BEGIN ...@@ -98,7 +98,7 @@ BEGIN
BEGIN BEGIN
v := r; v := r;
v.out_sosi_ctrl := c_dp_sosi_rst; v.out_sosi_ctrl := c_dp_sosi_rst;
mm_mosi.rd <= '0'; v.mm_mosi.rd := '0';
-- initiate next block and capture in_sosi strobe -- initiate next block and capture in_sosi strobe
IF r.busy = '0' AND in_sosi.sop = '1' THEN IF r.busy = '0' AND in_sosi.sop = '1' THEN
...@@ -106,8 +106,8 @@ BEGIN ...@@ -106,8 +106,8 @@ BEGIN
v.in_sosi_strobe := in_sosi; v.in_sosi_strobe := in_sosi;
ELSIF r.busy = '1' THEN ELSIF r.busy = '1' THEN
-- continue with block -- continue with block
mm_mosi.rd <= '1'; v.mm_mosi.rd := '1';
mm_mosi.address <= TO_MEM_ADDRESS(r.crosslets_index * g_nof_signal_inputs + r.in_b_index); -- streams iterate over in_b_index v.mm_mosi.address := TO_MEM_ADDRESS(r.crosslets_index * g_nof_signal_inputs + r.in_b_index); -- streams iterate over in_b_index
-- Indices counters to select data order -- Indices counters to select data order
IF r.in_b_index < g_nof_signal_inputs - 1 THEN IF r.in_b_index < g_nof_signal_inputs - 1 THEN
......
...@@ -69,9 +69,12 @@ ARCHITECTURE str OF st_xst IS ...@@ -69,9 +69,12 @@ ARCHITECTURE str OF st_xst IS
busy : STD_LOGIC; busy : STD_LOGIC;
in_a_index : NATURAL; in_a_index : NATURAL;
in_b_index : NATURAL; in_b_index : NATURAL;
reg_x_sosi_0_re : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
reg_x_sosi_0_im : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
in_a_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
END RECORD; END RECORD;
CONSTANT c_reg_rst : t_reg := ('0', 0, 0); CONSTANT c_reg_rst : t_reg := ('0', 0, 0, (OTHERS=>(OTHERS => '0')), (OTHERS=>(OTHERS => '0')), (OTHERS => c_dp_sosi_rst) );
SIGNAL r : t_reg; SIGNAL r : t_reg;
SIGNAL nxt_r : t_reg; SIGNAL nxt_r : t_reg;
...@@ -80,8 +83,6 @@ ARCHITECTURE str OF st_xst IS ...@@ -80,8 +83,6 @@ ARCHITECTURE str OF st_xst IS
SIGNAL in_b_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); SIGNAL in_b_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL x_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); SIGNAL x_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL reg_x_sosi_0_re : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
SIGNAL reg_x_sosi_0_im : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
BEGIN BEGIN
-- MM -> DP -- MM -> DP
...@@ -103,20 +104,7 @@ BEGIN ...@@ -103,20 +104,7 @@ BEGIN
-- in_b_sosi_arr = x_sosi_arr -- in_b_sosi_arr = x_sosi_arr
in_b_sosi_arr <= x_sosi_arr; in_b_sosi_arr <= x_sosi_arr;
in_a_sosi_arr <= nxt_r.in_a_sosi_arr;
-- Capture x_sosi_arr(0) data
reg_x_sosi_0_re(nxt_r.in_b_index) <= x_sosi_arr(0).re;
reg_x_sosi_0_im(nxt_r.in_b_index) <= x_sosi_arr(0).im;
-- reorder x_sosi_arr(0) data to follow in_a_index instead of in_b_index. All sosi in in_a_sosi_arr are identical.
p_in_a : PROCESS(x_sosi_arr, reg_x_sosi_0_re, reg_x_sosi_0_im, nxt_r.in_a_index)
BEGIN
FOR I IN 0 TO g_nof_streams-1 LOOP
in_a_sosi_arr(I) <= x_sosi_arr(0);
in_a_sosi_arr(I).re <= reg_x_sosi_0_re(nxt_r.in_a_index);
in_a_sosi_arr(I).im <= reg_x_sosi_0_im(nxt_r.in_a_index);
END LOOP;
END PROCESS;
-- Register process -- Register process
p_reg : PROCESS(dp_rst, dp_clk) p_reg : PROCESS(dp_rst, dp_clk)
...@@ -128,11 +116,19 @@ BEGIN ...@@ -128,11 +116,19 @@ BEGIN
END IF; END IF;
END PROCESS; END PROCESS;
-- Combinatorial process to create in_a_index and in_b_index for reoredering x_sosi_arr(0) data. -- Combinatorial process to create in_a_index and in_b_index and reoredering x_sosi_arr(0) data.
p_comb : PROCESS(r, x_sosi_arr) p_comb : PROCESS(r, x_sosi_arr)
VARIABLE v : t_reg; VARIABLE v : t_reg;
VARIABLE v_in_a_index : NATURAL;
VARIABLE v_in_b_index : NATURAL;
VARIABLE v_reg_x_sosi_0_re : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
VARIABLE v_reg_x_sosi_0_im : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
BEGIN BEGIN
v := r; v := r;
v_in_a_index := r.in_a_index;
v_in_b_index := r.in_b_index;
v_reg_x_sosi_0_re := r.reg_x_sosi_0_re;
v_reg_x_sosi_0_im := r.reg_x_sosi_0_im;
-- initiate next block -- initiate next block
IF r.busy = '0' AND x_sosi_arr(0).sop = '1' THEN IF r.busy = '0' AND x_sosi_arr(0).sop = '1' THEN
v.busy := '1'; v.busy := '1';
...@@ -140,22 +136,39 @@ BEGIN ...@@ -140,22 +136,39 @@ BEGIN
ELSIF r.busy = '1' THEN ELSIF r.busy = '1' THEN
-- Indices counters to select data order -- Indices counters to select data order
IF r.in_b_index < g_nof_signal_inputs - 1 THEN IF r.in_b_index < g_nof_signal_inputs - 1 THEN
v.in_b_index := r.in_b_index + 1; v_in_b_index := r.in_b_index + 1;
ELSE ELSE
v.in_b_index := 0; v_in_b_index := 0;
IF r.in_a_index < g_nof_signal_inputs - 1 THEN IF r.in_a_index < g_nof_signal_inputs - 1 THEN
v.in_a_index := r.in_a_index + 1; v_in_a_index := r.in_a_index + 1;
ELSE ELSE
v.in_a_index := 0; v_in_a_index := 0;
END IF; END IF;
END IF; END IF;
END IF; END IF;
-- End of block -- End of block
IF x_sosi_arr(0).eop = '1' THEN IF x_sosi_arr(0).eop = '1' THEN
v.busy := '0'; v.busy := '0';
v.in_a_index := 0; v_in_a_index := 0;
v.in_b_index := 0; v_in_b_index := 0;
END IF; END IF;
-- Capture x_sosi_arr(0) data
v_reg_x_sosi_0_re(v_in_b_index) := x_sosi_arr(0).re;
v_reg_x_sosi_0_im(v_in_b_index) := x_sosi_arr(0).im;
-- reorder x_sosi_arr(0) data to follow in_a_index instead of in_b_index. All sosi in in_a_sosi_arr are identical.
FOR I IN 0 TO g_nof_streams-1 LOOP
v.in_a_sosi_arr(I) := x_sosi_arr(0);
v.in_a_sosi_arr(I).re := v_reg_x_sosi_0_re(v_in_a_index);
v.in_a_sosi_arr(I).im := v_reg_x_sosi_0_im(v_in_a_index);
END LOOP;
v.in_a_index := v_in_a_index;
v.in_b_index := v_in_b_index;
v.reg_x_sosi_0_re := v_reg_x_sosi_0_re;
v.reg_x_sosi_0_im := v_reg_x_sosi_0_im;
nxt_r <= v; nxt_r <= v;
END PROCESS; END PROCESS;
......
...@@ -101,3 +101,34 @@ peripherals: ...@@ -101,3 +101,34 @@ peripherals:
mm_width: 32 mm_width: 32
user_width: g_stat_data_w user_width: g_stat_data_w
radix: uint64 radix: uint64
- peripheral_name: st_xst_for_sdp # pi_st_xst.py
peripheral_description: |
"Accumulate the beamlet auto power values during a sync interval for the beamlet statistics (BST) in LOFAR2.0 SDP"
parameters:
# Parameters of pi_st_bst.py, fixed in node_sdp_beamformer.vhd / sdp_pkg.vhd
- { name: g_nof_instances, value: 6 }
# Parameters of st_sst.vhd, fixed in node_sdp_filterbank.vhd / sdp_pkg.vhd
- { name: g_nof_stat, value: 976 } # nof accumulators: S_sub_bf * N_pol_bf = 488 * 2 = 976
- { name: g_stat_data_w, value: 54 } # statistics accumulator user_width in bits: W_statistic = 64
- { name: g_stat_data_sz, value: 2 } # statistics accumulator user_width in 32b MM words: W_statistic_sz = 2
mm_ports:
# MM port for st_sst.vhd
- mm_port_name: RAM_ST_SST
mm_port_type: RAM
mm_port_description: |
"The beamlet statistics per PN are stored in 1 block of S_sub_bf * N_pol_bf = 488 * 2 = 976 real values as:
(uint64)BST[g_nof_stat] = (uint64)BST[S_sub_bf][N_pol_bf]
where N_pol_bf = 2 and S_sub_bf = 488 are defined in sdp_pkg.vhd."
number_of_mm_ports: 1
fields:
- - field_name: power
field_description: ""
number_of_fields: g_nof_stat * g_stat_data_sz
address_offset: 0x0
mm_width: 32
user_width: g_stat_data_w
radix: cint64_ir
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment