Removed common_top.vhd and dp_top.vhd from the hdllib.cfg. Such top level...

Removed common_top.vhd and dp_top.vhd from the hdllib.cfg. Such top level components for trial synthesis need to have their own unb1_<name> or unb2_<name> or stratixiv_<name> directory with hdllib.cfg in designs/.

libraries/base/common/hdllib.cfg

@@ -159,8 +159,6 @@ synth_files =
     src/vhdl/avs_common_mm_readlatency2.vhd
     src/vhdl/avs_common_reg_r_w.vhd
     
-    build/synth/quartus/common_top.vhd
-
     tb/vhdl/tb_common_pkg.vhd
     tb/vhdl/tb_common_mem_pkg.vhd
     

libraries/base/dp/hdllib.cfg

@@ -119,7 +119,6 @@ synth_files =
     tb/vhdl/dp_stream_recorder.vhd
     tb/vhdl/dp_stream_rec_play.vhd
     
-    build/synth/quartus/dp_top.vhd
     tb/vhdl/tb_dp_pkg.vhd
     
 test_bench_files =