Merge branch 'L2SDP-75' into 'master'

Resolve L2SDP-75

Closes L2SDP-75

See merge request desp/hdl!50

applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/lofar2_unb2b_filterbank_256MHz.sdc

+###############################################################################
+#
+# Copyright (C) 2018
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+# Constrain the input I/O path
+#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -max 3 [all_inputs]
+#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -min 2 [all_inputs]
+# Constrain the output I/O path
+#set_output_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -max 3 [all_inputs]
+#set_output_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -min 2 [all_inputs]
+
+
+# False path the PPS to DDIO:
+#set_input_delay  -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 3 [get_ports {PPS}]
+#set_false_path -from {PPS} -to {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr}; set_false_path -from {PPS} -to {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr}
+
+
+#set_false_path -from [get_ports {PPS}] -to [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}]
+
+#set_input_delay -min -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 2 [get_ports {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap}]
+#set_input_delay -max -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 4 [get_ports {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap}]
+
+#set_false_path -from {PPS} -to {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio*}
+
+
+
+set_time_format -unit ns -decimal_places 3
+
+create_clock -period 125Mhz [get_ports {ETH_CLK}]
+create_clock -period 256Mhz [get_ports {CLK}]
+create_clock -period 100Mhz [get_ports {CLKUSR}]
+create_clock -period 644.53125Mhz [get_ports {SA_CLK}]
+create_clock -period 644.53125Mhz [get_ports {SB_CLK}]
+create_clock -period 200MHz -name {BCK_REF_CLK} { BCK_REF_CLK }
+
+# Create altera reserved tck to solve unconstrained clock warning.
+create_clock -period "100.000 ns" -name {altera_reserved_tck} {altera_reserved_tck}
+
+derive_pll_clocks
+derive_clock_uncertainty
+
+set_clock_groups -asynchronous -group {CLK}
+set_clock_groups -asynchronous -group {BCK_REF_CLK}
+set_clock_groups -asynchronous -group {CLK_USR}
+set_clock_groups -asynchronous -group {CLKUSR}
+set_clock_groups -asynchronous -group {SA_CLK}
+set_clock_groups -asynchronous -group {SB_CLK}
+# Do not put ETH_CLK in this list, otherwise the Triple Speed Ethernet does not work
+
+# Altera temp sense clock
+set_clock_groups -asynchronous -group [get_clocks altera_ts_clk]
+
+# ALtera JTAG clock
+set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck]
+
+# IOPLL outputs (which have global names defined in the IP qsys settings)
+set_clock_groups -asynchronous -group [get_clocks pll_clk20]
+set_clock_groups -asynchronous -group [get_clocks pll_clk50]
+set_clock_groups -asynchronous -group [get_clocks pll_clk100]
+set_clock_groups -asynchronous -group [get_clocks pll_clk125]
+set_clock_groups -asynchronous -group [get_clocks pll_clk200]
+set_clock_groups -asynchronous -group [get_clocks pll_clk200p]
+set_clock_groups -asynchronous -group [get_clocks pll_clk400]
+
+
+# FPLL outputs
+#set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk0}]
+#set_clock_groups -asynchronous -group [get_clocks {*mac_clock*xcvr_fpll_a10_0|outclk0}]
+#set_clock_groups -asynchronous -group [get_clocks {*dp_clk*xcvr_fpll_a10_0|outclk0}]
+#set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk1}]
+set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk3}]
+
+
+set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_native_insts[*]|rx_pma_clk}]
+
+#set_false_path -from {*u_rst200|u_async|din_meta[2]} -to {*FIFOram*}
+
+#set_clock_groups -asynchronous \
+#-group [get_clocks {inst2|xcvr_4ch_native_phy_inst|xcvr_native_a10_0|g_xcvr_native_insts[?]|rx_pma_clk}] \
+#-group [get_clocks {inst2|xcvr_pll_inst|xcvr_fpll_a10_0|tx_bonding_clocks[0]}]
+
+# false paths added for the jesd test design
+set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|link_clk}]
+set_false_path -from [get_clocks {*core_pll|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|frame_clk}]
+set_false_path -from [get_clocks {*core_pll|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]

applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/hdllib.cfg

+hdl_lib_name = lofar2_unb2b_filterbank_full_256MHz
+hdl_library_clause_name = lofar2_unb2b_filterbank_full_256MHz_lib
+hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_filterbank 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e1sg
+                     
+ synth_files =
+    lofar2_unb2b_filterbank_full_256MHz.vhd
+
+test_bench_files = 
+
+regression_test_vhdl =
+
+
+[modelsim_project_file]
+modelsim_copy_files =
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+    ../../quartus .
+    ../../src/data data
+quartus_qsf_files =
+    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+# use lofar2_unb2b_filterbank.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
+quartus_sdc_files =
+    ../../quartus/lofar2_unb2b_filterbank_256MHz.sdc
+    #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+    ../../quartus/lofar2_unb2b_filterbank_pins.tcl
+
+quartus_vhdl_files = 
+
+quartus_qip_files =
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank_full_256MHz/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank.qip
+
+quartus_ip_files =
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_common_mm_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_common_mm_1.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_eth_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_clk_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_cpu_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jesd204b.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jtag_uart_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_onchip_memory2_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_pps.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_aduh_monitor.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_fil_coefs.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_scrap.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_st_sst.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_wg.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_aduh_monitor.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_source.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_data.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_selector.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_shiftram.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_epcs.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_data.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_remu.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_si.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_pmbus.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wg.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_rom_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_timer_0.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2

applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author : R. van der Walle
+-- Purpose:  
+--   Wrapper for full filterbank test design
+-- Description:
+--   Unb2b version for lab testing
+--   Contains complete AIT input stage with 12 ADC streams and FSUB
+
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_filterbank_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY lofar2_unb2b_filterbank_full_256MHz IS
+  GENERIC (
+    g_design_name      : STRING  := "lofar2_unb2b_filterbank_full_256MHz";
+    g_design_note      : STRING  := "Lofar2 filterbank with all streams on 256MHz ext clk";
+    g_sim              : BOOLEAN := FALSE; --Overridden by TB
+    g_sim_unb_nr       : NATURAL := 0;
+    g_sim_node_nr      : NATURAL := 0;
+    g_stamp_date       : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
+    g_stamp_time       : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
+    g_revision_id      : STRING := ""   -- revision ID     -- set by QSF
+  );
+  PORT (
+    -- GENERAL
+    CLK          : IN    STD_LOGIC; -- System Clock
+    PPS          : IN    STD_LOGIC; -- System Sync
+    WDI          : OUT   STD_LOGIC; -- Watchdog Clear
+    INTA         : INOUT STD_LOGIC; -- FPGA interconnect line
+    INTB         : INOUT STD_LOGIC; -- FPGA interconnect line
+
+    -- Others
+    VERSION      : IN    STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+    ID           : IN    STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+    TESTIO       : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
+    
+    -- I2C Interface to Sensors
+    SENS_SC      : INOUT STD_LOGIC;
+    SENS_SD      : INOUT STD_LOGIC;
+  
+    PMBUS_SC     : INOUT STD_LOGIC;
+    PMBUS_SD     : INOUT STD_LOGIC;
+    PMBUS_ALERT  : IN    STD_LOGIC := '0';
+
+    -- 1GbE Control Interface
+    ETH_CLK      : IN    STD_LOGIC;
+    ETH_SGIN     : IN    STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+    ETH_SGOUT    : OUT   STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+
+    -- LEDs
+    QSFP_LED     : OUT   STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+
+     -- back transceivers (note only 6 are used in unb2b)
+    BCK_RX       : IN    STD_LOGIC_VECTOR(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b-1  downto c_unb2b_board_nof_tr_jesd204b);
+    BCK_REF_CLK  : IN    STD_LOGIC; -- Use as JESD204B_REFCLK
+ 
+    -- jesd204b syncronization signals (2 syncs)
+    JESD204B_SYSREF : IN    STD_LOGIC;
+    JESD204B_SYNC_N : OUT   STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0)
+  );
+END lofar2_unb2b_filterbank_full_256MHz;
+ 
+ARCHITECTURE str OF lofar2_unb2b_filterbank_full_256MHz IS
+
+  SIGNAL JESD204B_SERIAL_DATA       : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1  downto 0);
+  SIGNAL jesd204b_sync_n_arr        : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1  downto 0);
+  SIGNAL JESD204B_REFCLK            : STD_LOGIC;
+
+
+BEGIN
+
+  -- Mapping between JESD signal names and UNB2B pin/schematic names
+  JESD204B_REFCLK <=  BCK_REF_CLK;
+  JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
+  JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
+  JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
+  JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
+  JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
+  JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
+  JESD204B_SERIAL_DATA(6) <= '0';
+  JESD204B_SERIAL_DATA(7) <= '0';
+  JESD204B_SERIAL_DATA(8) <= '0';
+  JESD204B_SERIAL_DATA(9) <= '0';
+  JESD204B_SERIAL_DATA(10) <= '0';
+  JESD204B_SERIAL_DATA(11) <= '0';
+  JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
+
+
+  u_revision : ENTITY lofar2_unb2b_filterbank_lib.lofar2_unb2b_filterbank
+  GENERIC MAP (
+    g_design_name => g_design_name,
+    g_design_note => g_design_note,
+    g_sim         => g_sim,
+    g_sim_unb_nr  => g_sim_unb_nr,
+    g_sim_node_nr => g_sim_node_nr,
+    g_stamp_date  => g_stamp_date,
+    g_stamp_time  => g_stamp_time,
+    g_revision_id => g_revision_id
+  )
+  PORT MAP (
+    -- GENERAL
+    CLK          => CLK,
+    PPS          => PPS,
+    WDI          => WDI,
+    INTA         => INTA,
+    INTB         => INTB,
+
+    -- Others
+    VERSION      => VERSION,
+    ID           => ID,
+    TESTIO       => TESTIO,
+
+    -- I2C Interface to Sensors
+    SENS_SC      => SENS_SC,
+    SENS_SD      => SENS_SD,
+
+    PMBUS_SC     => PMBUS_SC,
+    PMBUS_SD     => PMBUS_SD,
+    PMBUS_ALERT  => PMBUS_ALERT,
+
+    -- 1GbE Control Interface
+    ETH_clk      => ETH_clk,
+    ETH_SGIN     => ETH_SGIN,
+    ETH_SGOUT    => ETH_SGOUT,
+
+    -- LEDs
+    QSFP_LED     => QSFP_LED,
+
+    -- back transceivers
+    JESD204B_SERIAL_DATA   => JESD204B_SERIAL_DATA,
+    JESD204B_REFCLK        => JESD204B_REFCLK,
+  
+    -- jesd204b syncronization signals
+    JESD204B_SYSREF        => JESD204B_SYSREF,
+    JESD204B_SYNC_N        => jesd204b_sync_n_arr
+  );
+END str;

applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd

@@ -104,6 +104,7 @@ ARCHITECTURE str OF lofar2_unb2b_filterbank IS
   -- Revision parameters
   CONSTANT c_revision_select        : t_lofar2_unb2b_filterbank_config := func_sel_revision_rec(g_design_name);
   CONSTANT c_nof_streams            : NATURAL := c_revision_select.nof_streams_input;    -- Streams actually passed through for processing
+  CONSTANT c_dp_clk_freq            : NATURAL := c_revision_select.dp_clk_freq;
 
   -- Firmware version x.y
   CONSTANT c_fw_version             : t_unb2b_board_fw_version := (1, 1);
@@ -279,6 +280,7 @@ BEGIN
     g_aux                => c_unb2b_board_aux,
     g_factory_image      => g_factory_image,
     g_protect_addr_range => g_protect_addr_range,
+    g_dp_clk_freq        => c_dp_clk_freq,
     g_dp_clk_use_pll     => FALSE
   )
   PORT MAP (

applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd

@@ -19,10 +19,11 @@
 --
 --------------------------------------------------------------------------------
 
-LIBRARY IEEE, common_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.numeric_std.ALL;
 USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
 
 PACKAGE lofar2_unb2b_filterbank_pkg IS
 
@@ -34,10 +35,12 @@ PACKAGE lofar2_unb2b_filterbank_pkg IS
     nof_streams_jesd204b           : NATURAL;  
     nof_streams_db                 : NATURAL;  
     nof_streams_input              : NATURAL; 
+    dp_clk_freq                    : NATURAL; 
   END RECORD;
 
   --                                                          nofjesd, nofdb, nofinput  
-  CONSTANT c_full             : t_lofar2_unb2b_filterbank_config := (     12,     2,       12 );
+  CONSTANT c_full             : t_lofar2_unb2b_filterbank_config := (     12,     2,       12, c_unb2b_board_ext_clk_freq_200M );
+  CONSTANT c_full_256MHz      : t_lofar2_unb2b_filterbank_config := (     12,     2,       12, c_unb2b_board_ext_clk_freq_256M );
 
   -- Function to select the revision configuration. 
   FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_lofar2_unb2b_filterbank_config;
@@ -51,6 +54,7 @@ PACKAGE BODY lofar2_unb2b_filterbank_pkg IS
   FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_lofar2_unb2b_filterbank_config IS
   BEGIN
     IF    g_design_name = "lofar2_unb2b_filterbank_full"        THEN RETURN c_full;
+    ELSIF g_design_name = "lofar2_unb2b_filterbank_full_256MHz" THEN RETURN c_full_256MHz;
     ELSE  RETURN c_full;
     END IF;
   END;

applications/lofar2/designs/lofar2_unb2c_filterbank/hdllib.cfg

+hdl_lib_name = lofar2_unb2c_filterbank
+hdl_library_clause_name = lofar2_unb2c_filterbank_lib
+hdl_lib_uses_synth = common technology mm unb2c_board dp eth tech_tse tr_10GbE diagnostics diag aduh wpfb tech_jesd204b lofar2_sdp
+hdl_lib_uses_sim =  
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd
+    src/vhdl/lofar2_unb2c_filterbank_pkg.vhd
+    src/vhdl/mmm_lofar2_unb2c_filterbank.vhd
+    src/vhdl/lofar2_unb2c_filterbank.vhd
+    
+test_bench_files = 
+    tb/vhdl/tb_lofar2_unb2c_filterbank.vhd
+
+regression_test_vhdl =
+    tb/vhdl/tb_lofar2_unb2c_filterbank.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+     src/data data
+
+[quartus_project_file]
+quartus_copy_files =
+    quartus .
+