25MHz for mm_clk at simulation

boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd

 -------------------------------------------------------------------------------
 --
--- Copyright (C) 2012
+-- Copyright (C) 2015
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
 -- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
@@ -72,7 +72,7 @@ ARCHITECTURE str OF unb2_minimal IS
 
   -- Firmware version x.y
   CONSTANT c_fw_version             : t_unb2_board_fw_version := (1, 1);
-  CONSTANT c_mm_clk_freq            : NATURAL := c_unb2_board_mm_clk_freq_50M;
+  CONSTANT c_mm_clk_freq            : NATURAL := sel_a_b(g_sim,c_unb2_board_mm_clk_freq_25M,c_unb2_board_mm_clk_freq_50M);
 
   -- System
   SIGNAL cs_sim                     : STD_LOGIC;
@@ -319,11 +319,6 @@ BEGIN
   PORT MAP (
     rst             => mm_rst,
     clk             => mm_clk,
-    -- internal pulser outputs
-    --pulse_us        => pulse_us,
-    --pulse_ms        => pulse_ms,
-    --pulse_s         => pulse_s,
-    -- leds
     green_led_arr   => qsfp_green_led_arr,
     red_led_arr     => qsfp_red_led_arr
   );
@@ -338,10 +333,5 @@ BEGIN
     QSFP_LED      => QSFP_LED
   );
 
-  -----------------------------------------------------------------------------
-  -- Node function
-  -----------------------------------------------------------------------------
-  -- Insert node_[design_name] here
-
 END str;