Introduced g_delayed_lo to be able to specify the delay more finely.

libraries/base/common/src/vhdl/common_stable_delayed.vhd

@@ -29,15 +29,21 @@ USE common_lib.common_pkg.ALL;
 -- Description:
 --   This function can be used to filter out temporary toggling in r_in. The
 --   r_stable only becomes active after r_in has remained active for 
---   2**(g_delayed_w-1) clk cycles. The r_stable always goes inactive when
---   r_in is inactive. The active level can be set with g_active_level to '1'
---   or '0'.
+--   2**g_delayed_w - 2**g_delayed_lo clk cycles. The r_stable always goes
+--   inactive when r_in is inactive.
+--   The active level can be set with g_active_level to '1' or '0'.
 -- Remarks:
+-- . Verified with tb_lvdsh_dd_phs4.vhd, because there this was used first.
+-- . Instead of the combination of g_delayed_w and g_delayed_lo a single
+--   g_delayed NATURAL could have been used to exactly specify the delay.
+--   However then delays larger than 2**31 would be complicated due to the
+--   limited 31 bit range of a NATURAL in VHDL.
 
 ENTITY common_stable_delayed IS
   GENERIC (
     g_active_level : STD_LOGIC := '1';
-    g_delayed_w    : NATURAL := 8
+    g_delayed_w    : NATURAL := 8;
+    g_delayed_lo   : NATURAL := 7    -- choose <= g_delayed_hi = g_delayed_w-1
   );
   PORT (
     rst          : IN  STD_LOGIC;
@@ -65,7 +71,17 @@ BEGIN
   r_stable <= p_stable WHEN g_active_level='1' ELSE NOT p_stable;
   
   cnt_clr <= NOT p_in;
-  cnt_en  <= NOT cnt(cnt'HIGH);
+  
+  p_clk : PROCESS(rst, clk)
+  BEGIN
+    IF rst='1' THEN
+      cnt_en   <= '0';
+      p_stable <= '0';
+    ELSIF rising_edge(clk) THEN
+      cnt_en   <= NOT vector_and(cnt(g_delayed_w-1 DOWNTO g_delayed_lo));
+      p_stable <=     vector_and(cnt(g_delayed_w-1 DOWNTO g_delayed_lo));
+    END IF;
+  END PROCESS;
   
   u_common_counter : ENTITY common_lib.common_counter
   GENERIC MAP (
@@ -79,6 +95,4 @@ BEGIN
     count   => cnt
   );
 
-  p_stable <= cnt(cnt'HIGH);
-    
 END rtl;