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Commit f4095c52 authored by Daniel van der Schuur's avatar Daniel van der Schuur
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Update: Removed MM control, added DP->MM RAM blocks. 

All code compiles and passes the test benches in simulation.

Committed  changes to branch L2SDP-136:

st_histogram_reg.vhd:
- deleted as it is no longer required

st_histogram.vhd:
- Removed ram_clearing status output

mms_st_histogram.vhd:
-removed reg_mosi/reg_miso
-replaced single common_ram_cr_cw with  g_nof_instances common_ram_cr_cw
-added common_mem_mux
-replaced per-instance readout control logic with readout control for all g_nof_instances in parallel (triggered by snk_in.sync)

tb_mms_st_histogram.vhd:
-Stripped out the per-instance readout control code
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1 merge request!137st_histogram updates. Ready for integration in LOFAR2.
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-------------------------------------------------------------------------------
--
-- Copyright 2020
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-------------------------------------------------------------------------------
-- Author:
-- . Daniel van der Schuur
-- Purpose:
-- . Provide MM registers for st_histogram
-- Description:
-- . Address 0, bit 0 = RAM clear
-- . Read : 'ram_clearing' status output of st_histogram.vhd. '1' when RAM is clearing.
-- . Address 1 = select RAM instance to fill (read out)
-- . Read : read back selected instance
-- . Write: select RAM instance to fill
-- . Address 2, bit 0 = RAM fill
-- . Read : 'ram_filling' status. '1' right after write of ram_fill. '0' when not filling RAM (anymore).
-- . Write: 'ram_fill ' control. '1' to fill RAM on write event.
LIBRARY IEEE, common_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
ENTITY st_histogram_reg IS
GENERIC (
g_nof_instances : NATURAL
);
PORT (
dp_clk : IN STD_LOGIC;
dp_rst : IN STD_LOGIC;
ram_clearing : IN STD_LOGIC;
ram_fill_inst : OUT STD_LOGIC_VECTOR(ceil_log2(g_nof_instances)-1 DOWNTO 0);
ram_fill : OUT STD_LOGIC;
ram_filling : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
mm_rst : IN STD_LOGIC;
reg_mosi : IN t_mem_mosi;
reg_miso : OUT t_mem_miso
);
END st_histogram_reg;
ARCHITECTURE rtl OF st_histogram_reg IS
CONSTANT c_nof_addresses : NATURAL := 3;
CONSTANT c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_nof_addresses),
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
nof_dat => c_nof_addresses,
init_sl => '0');
SIGNAL mm_ram_clearing : STD_LOGIC;
SIGNAL mm_ram_fill_inst : STD_LOGIC_VECTOR(ceil_log2(g_nof_instances)-1 DOWNTO 0);
SIGNAL mm_ram_fill : STD_LOGIC;
SIGNAL mm_ram_filling : STD_LOGIC;
BEGIN
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
-- . Hardcode the shared MM slave register directly in RTL instead of using
-- the common_reg_r_w instance. Directly using RTL is easier when the large
-- MM register has multiple different fields and with different read and
-- write options per field in one MM register.
------------------------------------------------------------------------------
p_mm_reg : PROCESS (mm_clk, mm_rst)
BEGIN
IF mm_rst = '1' THEN
-- Read access
reg_miso <= c_mem_miso_rst;
-- Access event, register values
mm_ram_fill <= '0';
mm_ram_fill_inst <= (OTHERS=>'0');
ELSIF rising_edge(mm_clk) THEN
-- Read access defaults
reg_miso.rdval <= '0';
-- Access event defaults
mm_ram_fill <= '0';
-- Write access: set register value
IF reg_mosi.wr = '1' THEN
CASE TO_UINT(reg_mosi.address(c_mm_reg.adr_w-1 DOWNTO 0)) IS
WHEN 1 =>
mm_ram_fill_inst <= reg_mosi.wrdata(ceil_log2(g_nof_instances)-1 DOWNTO 0);
WHEN 2 =>
mm_ram_fill <= '1';
WHEN OTHERS => NULL; -- unused MM addresses
END CASE;
-- Read access: get register value
ELSIF reg_mosi.rd = '1' THEN
reg_miso <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
reg_miso.rdval <= '1'; -- c_mm_reg.latency = 1
CASE TO_UINT(reg_mosi.address(c_mm_reg.adr_w-1 DOWNTO 0)) IS
WHEN 0 =>
-- Read RAM clearing status
reg_miso.rddata(0) <= mm_ram_clearing;
WHEN 1 =>
-- Read selected RAM instance to fill
reg_miso.rddata(ceil_log2(g_nof_instances)-1 DOWNTO 0) <= mm_ram_fill_inst;
WHEN 2 =>
-- Read RAM filling status
reg_miso.rddata(0) <= mm_ram_filling;
WHEN OTHERS => NULL; -- unused MM addresses
END CASE;
END IF;
END IF;
END PROCESS;
------------------------------------------------------------------------------
-- Transfer register value between mm_clk and st_clk domain.
-- If the function of the register ensures that the value will not be used
-- immediately when it was set, then the transfer between the clock domains
-- can be done by wires only. Otherwise if the change in register value can
-- have an immediate effect then the bit or word value needs to be transfered
-- using:
--
-- . common_async --> for single-bit level signal
-- . common_spulse --> for single-bit pulse signal
-- . common_reg_cross_domain --> for a multi-bit (a word) signal
--
-- Typically always use a crossing component for the single bit signals (to
-- be on the save side) and only use a crossing component for the word
-- signals if it is necessary (to avoid using more logic than necessary).
------------------------------------------------------------------------------
-- ST --> MM
u_common_async_clear : ENTITY common_lib.common_async
GENERIC MAP (
g_rst_level => '0'
)
PORT MAP (
clk => mm_clk,
rst => mm_rst,
din => ram_clearing,
dout => mm_ram_clearing
);
u_common_async_fill : ENTITY common_lib.common_async
GENERIC MAP (
g_rst_level => '0'
)
PORT MAP (
clk => mm_clk,
rst => mm_rst,
din => ram_filling,
dout => mm_ram_filling
);
u_common_spulse_fill : ENTITY common_lib.common_spulse
PORT MAP (
in_clk => mm_clk,
in_rst => mm_rst,
in_pulse => mm_ram_fill,
in_busy => OPEN,
out_clk => dp_clk,
out_rst => dp_rst,
out_pulse => ram_fill
);
u_common_reg_cross_domain : ENTITY common_lib.common_reg_cross_domain
PORT MAP (
in_clk => mm_clk,
in_rst => mm_rst,
in_dat => mm_ram_fill_inst,
in_done => OPEN,
out_clk => dp_clk,
out_rst => dp_rst,
out_dat => ram_fill_inst,
out_new => OPEN
);
END rtl;
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