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RTSD
HDL
Commits
f401f816
Commit
f401f816
authored
4 years ago
by
Eric Kooistra
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Added radix: char for strings.
parent
ba0ca36f
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2 merge requests
!100
Removed text for XSub that is now written in Confluence Subband correlator...
,
!71
Resolve L2SDP-186
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boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
+5
-7
5 additions, 7 deletions
...board2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
with
5 additions
and
7 deletions
boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
+
5
−
7
View file @
f401f816
...
...
@@ -35,6 +35,7 @@ peripherals:
access_mode
:
RO
address_offset
:
0x0
number_of_fields
:
8192
# c_rom_addr_w in mms_unb2b_board_system_info
radix
:
char
# MM port for mms_unb2b_board_system_info.vhd / unb2b_board_system_info_reg.vhd
-
slave_name
:
PIO_SYSTEM_INFO
...
...
@@ -102,12 +103,7 @@ peripherals:
access_mode
:
RO
address_offset
:
0x8
number_of_fields
:
13
#- - field_name: design_name
# field_description: "FPGA FW design name string."
# width: 416 # = 13 * 32b = 52 char # EK: TODO width > 32 is allowed
# access_mode: RO
# address_offset: 0x8
# number_of_fields: 1
radix
:
char
-
-
field_name
:
stamp_date
field_description
:
"
FPGA
FW
compile
date
string."
access_mode
:
RO
...
...
@@ -123,11 +119,13 @@ peripherals:
access_mode
:
RO
address_offset
:
0x44
number_of_fields
:
3
radix
:
hexadecimal
-
-
field_name
:
design_note
field_description
:
"
FPGA
FW
design
note
string."
access_mode
:
RO
address_offset
:
0x50
number_of_fields
:
13
number_of_fields
:
13
radix
:
char
-
peripheral_name
:
wdi
# pi_wdi.py
peripheral_description
:
"
"
...
...
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