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RTSD
HDL
Commits
f2f9d30e
Commit
f2f9d30e
authored
10 years ago
by
Daniel van der Schuur
Browse files
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Plain Diff
-Moved mixed width FIFO;
-Reverified and -validated dp_offload_tx.
parent
9dd04473
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applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd
+28
-30
28 additions, 30 deletions
...rtif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd
with
28 additions
and
30 deletions
applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd
+
28
−
30
View file @
f2f9d30e
...
@@ -191,9 +191,9 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
...
@@ -191,9 +191,9 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
CONSTANT
c_offload_bg_ctrl
:
t_diag_block_gen
:
=
(
'1'
,
-- enable
CONSTANT
c_offload_bg_ctrl
:
t_diag_block_gen
:
=
(
'1'
,
-- enable
'0'
,
-- enable_sync
'0'
,
-- enable_sync
TO_UVEC
(
6
00
,
c_diag_bg_samples_per_packet_w
),
TO_UVEC
(
3
00
,
c_diag_bg_samples_per_packet_w
),
TO_UVEC
(
64
,
c_diag_bg_blocks_per_sync_w
),
TO_UVEC
(
64
,
c_diag_bg_blocks_per_sync_w
),
TO_UVEC
(
24414-
6
00
,
c_diag_bg_gapsize_w
),
TO_UVEC
(
24414-
3
00
,
c_diag_bg_gapsize_w
),
TO_UVEC
(
0
,
c_diag_bg_mem_low_adrs_w
),
TO_UVEC
(
0
,
c_diag_bg_mem_low_adrs_w
),
TO_UVEC
(
0
,
c_diag_bg_mem_high_adrs_w
),
TO_UVEC
(
0
,
c_diag_bg_mem_high_adrs_w
),
TO_UVEC
(
0
,
c_diag_bg_bsn_init_w
));
TO_UVEC
(
0
,
c_diag_bg_bsn_init_w
));
...
@@ -307,8 +307,7 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
...
@@ -307,8 +307,7 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
-- 1GbE Visibility Offload
-- 1GbE Visibility Offload
SIGNAL
dp_fifo_dc_mixed_widths_snk_in
:
t_dp_sosi
;
SIGNAL
dp_fifo_dc_mixed_widths_snk_in
:
t_dp_sosi
;
SIGNAL
dp_fifo_dc_mixed_widths_src_out
:
t_dp_sosi
;
SIGNAL
dp_fifo_dc_mixed_widths_src_in
:
t_dp_siso
;
SIGNAL
apertif_unb1_correlator_vis_offload_snk_in
:
t_dp_sosi
;
SIGNAL
apertif_unb1_correlator_vis_offload_snk_in
:
t_dp_sosi
;
SIGNAL
apertif_unb1_correlator_vis_offload_snk_out
:
t_dp_siso
;
SIGNAL
apertif_unb1_correlator_vis_offload_snk_out
:
t_dp_siso
;
SIGNAL
dp_offload_tx_src_out_arr
:
t_dp_sosi_arr
(
1-1
DOWNTO
0
);
SIGNAL
dp_offload_tx_src_out_arr
:
t_dp_sosi_arr
(
1-1
DOWNTO
0
);
...
@@ -763,31 +762,6 @@ BEGIN
...
@@ -763,31 +762,6 @@ BEGIN
dp_fifo_dc_mixed_widths_snk_in
.
data
(
64-1
DOWNTO
0
)
<=
correlator_src_out_arr
(
0
)
.
re
(
64
/
2-1
DOWNTO
0
)
&
correlator_src_out_arr
(
0
)
.
im
(
64
/
2-1
DOWNTO
0
);
dp_fifo_dc_mixed_widths_snk_in
.
data
(
64-1
DOWNTO
0
)
<=
correlator_src_out_arr
(
0
)
.
re
(
64
/
2-1
DOWNTO
0
)
&
correlator_src_out_arr
(
0
)
.
im
(
64
/
2-1
DOWNTO
0
);
END
PROCESS
;
END
PROCESS
;
-----------------------------------------------------------------------------
-- 64b -> 32b
-----------------------------------------------------------------------------
u_dp_fifo_dc_mixed_widths
:
ENTITY
dp_lib
.
dp_fifo_dc_mixed_widths
GENERIC
MAP
(
g_wr_data_w
=>
64
,
g_rd_data_w
=>
32
,
g_use_ctrl
=>
TRUE
,
g_wr_fifo_size
=>
300
)
PORT
MAP
(
wr_rst
=>
dp_rst
,
wr_clk
=>
dp_clk
,
rd_rst
=>
dp_rst
,
rd_clk
=>
dp_clk
,
snk_in
=>
dp_fifo_dc_mixed_widths_snk_in
,
src_in
=>
dp_fifo_dc_mixed_widths_src_in
,
src_out
=>
dp_fifo_dc_mixed_widths_src_out
);
apertif_unb1_correlator_vis_offload_snk_in
<=
dp_fifo_dc_mixed_widths_src_out
;
dp_fifo_dc_mixed_widths_src_in
<=
apertif_unb1_correlator_vis_offload_snk_out
;
END
GENERATE
;
END
GENERATE
;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
...
@@ -799,6 +773,8 @@ BEGIN
...
@@ -799,6 +773,8 @@ BEGIN
g_nof_streams
=>
1
,
g_nof_streams
=>
1
,
g_use_tx_seq
=>
TRUE
,
g_use_tx_seq
=>
TRUE
,
g_use_bg_buffer_ram
=>
FALSE
,
g_use_bg_buffer_ram
=>
FALSE
,
g_buf_dat_w
=>
64
,
g_seq_dat_w
=>
64
,
g_diag_block_gen_rst
=>
c_offload_bg_ctrl
g_diag_block_gen_rst
=>
c_offload_bg_ctrl
)
)
PORT
MAP
(
PORT
MAP
(
...
@@ -808,10 +784,32 @@ BEGIN
...
@@ -808,10 +784,32 @@ BEGIN
dp_rst
=>
dp_rst
,
dp_rst
=>
dp_rst
,
dp_clk
=>
dp_clk
,
dp_clk
=>
dp_clk
,
out_sosi_arr
(
0
)
=>
apertif_unb1_correlator_vis_offload
_snk_in
out_sosi_arr
(
0
)
=>
dp_fifo_dc_mixed_widths
_snk_in
);
);
END
GENERATE
;
END
GENERATE
;
-----------------------------------------------------------------------------
-- 64b -> 32b
-----------------------------------------------------------------------------
u_dp_fifo_dc_mixed_widths
:
ENTITY
dp_lib
.
dp_fifo_dc_mixed_widths
GENERIC
MAP
(
g_wr_data_w
=>
64
,
g_rd_data_w
=>
32
,
g_use_ctrl
=>
TRUE
,
g_wr_fifo_size
=>
300
)
PORT
MAP
(
wr_rst
=>
dp_rst
,
wr_clk
=>
dp_clk
,
rd_rst
=>
dp_rst
,
rd_clk
=>
dp_clk
,
snk_in
=>
dp_fifo_dc_mixed_widths_snk_in
,
src_in
=>
apertif_unb1_correlator_vis_offload_snk_out
,
src_out
=>
apertif_unb1_correlator_vis_offload_snk_in
);
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- 1GbE visivility offload
-- 1GbE visivility offload
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
...
...
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