Updated text.

libraries/dsp/st/doc/st_histogram.txt

+
 Title: Develop histogram component in VHDL
-Author: E. Kooistra
+
+Author: E. Kooistra, ASTRON, dec 2019
 
 Contents:
 1) Purpose
 2) Requirements
 3) Design
 4) Development
-5) References:
+5) References
 
 
 1) Purpose
 
 The purpose of the component is to measure the histogram of ADC samples. The Python script
-try_histogram.py shows examples of histograms for typical ADC input signals:
+try_histogram.py [1] shows examples of histograms for typical ADC input signals.
 
  
 
 2) Requirements
 
 a) Data format
-The ADC samples arrive in a stream with the following fields:
+The ADC samples arrive in a stream with the following fields [2]:
 
 - data  : the samples
 - valid : new sample at this clock cycle
@@ -67,12 +69,12 @@ measurement sync interval.
 The histogram function is a statistics function and therefor it can be placed in the st/ HDL 
 library ($GIT/libraries/dsp/st/) and called st_histogram.vhd.
 
-The histogram component will need a double buffer. One buffer contains the bin counts that are 
-being updated during the current sync interval and the other buffer contains the bin counts
-that were preserved from the previous sync interval. The buffer is a block RAM. The highest 
-W bits of the input data are used as address to read the bin counter from the buffer, then 
+The histogram component will need a double buffer [3]. One buffer contains the bin counts that
+are being updated during the current sync interval and the other buffer contains the bin counts
+that were preserved from the previous sync interval. The buffer is a block RAM. The highest W
+bits of the input data are used as address to read the bin counter from the buffer, then 
 increment the bin counter, and then write the bin counter back into the buffer. This scheme
-resembles the approach that is used in the st_sst.vhd power statistics function in the ST
+resembles the approach that is used in the st_sst.vhd power statistics function [4] in the ST
 library. 
 
 The st_sst can integrate input samples continously without skipping samples. For the
@@ -88,6 +90,10 @@ occur during the first g_nof_bin samples of a sync interval and some addresses m
 during a entire sync interval (because these data values do not occur), but still the bin
 count at all addresses has to be cleared at the start of the sync interval.
 
+One M20k block RAM in Arria10 has 20kbit and can have maximum 40 bit wide data, so then it has
+20k / 40 = 512 addresses. With 32 bit data there are still 512 addreses. The st_histogram
+fits in one M20k block RAM if it uses g_nof_bins <= 256 (= 512 / 2, because of the dual page
+bin counts buffer).
 
 
 4) Development
@@ -97,7 +103,7 @@ All coding should be done on a branch in $GIT/hdl.
 a) In simulation
    - implement the st_histogram.vhd and a corresponding testbench tb_st_histogram.vhd
    - can use counter signal as test input or waveform generator (WG) to generate a sinus input.
-     The diag HDL library contains a WG.
+     The diag HDL library contains a WG [5].
 
 b) On hardware
    - create a design based on the UniBoard board support package (BSP = unb_minimal) with a diag
@@ -109,8 +115,8 @@ b) On hardware
 
 5) References
 
-a) $GIT/hdl/libraries/dsp/st/python/try_histogram.py
-b) $GIT/libraries/dsp/st/doc/ASTRON_RP_1397_Subband_Statistics_module.pdf  -- st_sst
-c) $GIT/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd  -- dual page buffer
-d) $GIT/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd   -- WG
-e) $GIT/libraries/base/dp/doc/ASTRON_RP_380_module_interface_records.pdf  -- streaming data (SOSI)
+[1] $GIT/hdl/libraries/dsp/st/python/try_histogram.py
+[2] $GIT/libraries/base/dp/doc/ASTRON_RP_380_module_interface_records.pdf  -- streaming data (SOSI)
+[3] $GIT/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd  -- dual page buffer
+[4] $GIT/libraries/dsp/st/doc/ASTRON_RP_1397_Subband_Statistics_module.pdf  -- st_sst
+[5] $GIT/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd   -- WG