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Commit f1832750 authored by Reinier van der Walle's avatar Reinier van der Walle
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added 200G ETH IP

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hdl_lib_name = tech_eth_200g
hdl_library_clause_name = tech_eth_200g_lib
hdl_lib_uses_synth = technology common dp tech_ip_agi027_1e1v_eth_200g
hdl_lib_uses_sim =
hdl_lib_technology =
#hdl_lib_disclose_library_clause_names =
# ip_agi027_1e1v_eth_200g ip_agi027_1e1v_eth_200g_lib
synth_files =
tech_eth_200g_component_pkg.vhd
tech_eth_200g_agi027_1e1v.vhd
tech_eth_200g.vhd
test_bench_files =
tb_tech_eth_200g.vhd
regression_test_vhdl =
[modelsim_project_file]
[quartus_project_file]
-------------------------------------------------------------------------------
--
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose:
-- . Test bench for tech_eth_200g and dp_offload_rx
-- Description:
-- u_tx u_rx
-- ___________________ ___________________
-- |tech_eth_200g | |dp_offload_rx |
-- stimuli_src -->| |--->| |--> verify_snk
-- | in out | | | in out |
-- |___________________| | |___________________|
-- |
-- link_offload_sosi
--
-- The verification of the header - data block boundary is controlled via
-- g_symbol_w:
-- . g_symbol_w = g_data_w : boundary at g_data_w
-- . g_symbol_w < g_data_w : boundary at g_symbol_w, by reducing the number
-- of the header dp_bsn field by 1 symbol. If the c_bsn_w <= 32 then the
-- header MM interface only needs one MM word to read the header, so
-- therefore there are two sizes of c_expected_tx_hdr_word_arr_* and
-- c_expected_rx_hdr_word_arr_*.
--
-- Remarks:
-- . The g_flow_control_verify has to be e_active, otherwise the tb fails,
-- probably due to limitation in dp_offload_rx.vhd.
-- . It appears that the tx_hdr_word read values are the MM write values, so
-- read of value from logic fields (with MM override '0', e.g. dp_bsn,
-- eth_src_mac) is not supported.
--
-- Usage:
-- > as 10
-- > run -all
--
library IEEE, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
use common_lib.common_lfsr_sequences_pkg.all;
use common_lib.common_mem_pkg.all;
use common_lib.common_field_pkg.all;
use common_lib.common_str_pkg.all;
use common_lib.tb_common_pkg.all;
use common_lib.tb_common_mem_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
entity tb_tech_eth_200g is
generic (
-- general
g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse; -- always e_active, e_random or e_pulse flow control
g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
g_print_en : boolean := true;
-- specific
g_data_w : natural := 512;
g_symbol_w : natural := 8;
g_empty : natural := 13; -- number of empty symbols in header when g_symbol_w < g_data_w, must be < c_nof_symbols_per_data
g_pkt_len : natural := 40;
g_pkt_gap : natural := 16
);
end tb_tech_eth_200g;
architecture tb of tb_tech_eth_200g is
constant c_mm_clk_period : time := 1 ns;
constant c_dp_clk_period : time := 5 ns;
constant c_ref_clk_period : time := 6.4 ns; --156.25MHz
-- Simulate header / payload boundary at g_data_w boundary or at g_symbol_w
-- boundary with one empty symbol, by adapting the size of the header dp_bsn
-- field:
-- . If g_symbol_w = g_data_w then boundary is at g_data_w, so empty is 0.
-- . If g_symbol_w < g_data_w then boundary is at last symbol, so empty is 1.
-- dp_stream_stimuli
constant c_stimuli_pulse_active : natural := 3;
constant c_stimuli_pulse_period : natural := 4;
-- dp_stream_verify
constant c_verify_pulse_active : natural := 1;
constant c_verify_pulse_period : natural := 5;
constant c_data_max : unsigned(g_data_w - 1 downto 0) := (others => '1');
constant c_dsp_max : unsigned(g_data_w - 1 downto 0) := (others => '1');
--CONSTANT c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := c_dp_sosi_unsigned_rst; -- default 0 is no wrap
constant c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := TO_DP_SOSI_UNSIGNED('0', '0', '0', '0', c_data_max, c_dsp_max, c_dsp_max, c_unsigned_0, c_unsigned_0, c_unsigned_0, c_unsigned_0);
constant c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones; -- default only accept increment +1
constant c_expected_pkt_len : natural := g_pkt_len;
constant c_sync_period : natural := 5;
constant c_sync_offset : natural := 2;
constant c_data_init : natural := 17;
constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := TO_DP_BSN(0);
constant c_nof_sync : natural := 3;
constant c_nof_packets : natural := c_sync_period * c_nof_sync;
constant c_hdr_len : natural := 7;
constant c_wait_last_evt : natural := 100 + c_nof_packets * c_hdr_len;
-----------------------------------------------------------------------------
-- Tx offload
-----------------------------------------------------------------------------
constant c_NODE_ID : std_logic_vector(7 downto 0) := TO_UVEC(0, 8);
signal id_backplane : std_logic_vector(c_byte_w - 1 downto 0);
signal id_chip : std_logic_vector(c_byte_w - 1 downto 0);
signal dp_fifo_sc_src_in : t_dp_siso := c_dp_siso_rdy;
signal dp_fifo_sc_src_out : t_dp_sosi;
signal dp_offload_tx_snk_in_arr : t_dp_sosi_arr(0 downto 0);
signal dp_offload_tx_snk_out_arr : t_dp_siso_arr(0 downto 0);
signal tx_hdr_fields_in_arr : t_slv_1024_arr(0 downto 0);
signal tx_hdr_fields_out_arr : t_slv_1024_arr(0 downto 0);
signal tx_hdr_word : std_logic_vector(c_word_w - 1 downto 0);
signal rx_hdr_word : std_logic_vector(c_word_w - 1 downto 0);
signal reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi := c_mem_mosi_rst;
signal reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
-----------------------------------------------------------------------------
-- Link
-----------------------------------------------------------------------------
signal serial_loopback : std_logic_vector(3 downto 0);
signal serial_loopback_n : std_logic_vector(3 downto 0);
-----------------------------------------------------------------------------
-- Rx offload
-----------------------------------------------------------------------------
signal dp_offload_rx_src_out_arr : t_dp_sosi_arr(0 downto 0);
signal dp_offload_rx_src_in_arr : t_dp_siso_arr(0 downto 0);
signal rx_hdr_fields_out_arr : t_slv_1024_arr(0 downto 0);
signal rx_hdr_fields_raw_arr : t_slv_1024_arr(0 downto 0);
signal reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi := c_mem_mosi_rst;
signal reg_dp_offload_rx_hdr_dat_miso : t_mem_miso;
-----------------------------------------------------------------------------
-- Test
-----------------------------------------------------------------------------
signal mm_clk : std_logic := '1';
signal mm_rst : std_logic := '1';
signal ninit_done : std_logic := '1';
signal dp_clk : std_logic := '1';
signal ref_clk : std_logic := '1';
signal dp_rst : std_logic := '1';
signal tb_end : std_logic := '0';
signal tx_pll_locked : std_logic := '0';
signal stimuli_src_in : t_dp_siso := c_dp_siso_rdy;
signal stimuli_src_out : t_dp_sosi;
signal stimuli_src_out_data : std_logic_vector(g_data_w - 1 downto 0);
signal verify_snk_in_enable : t_dp_sosi_sl := c_dp_sosi_sl_rst;
signal last_snk_in : t_dp_sosi;
signal last_snk_in_evt : std_logic;
signal verify_last_snk_in_evt : t_dp_sosi_sl := c_dp_sosi_sl_rst;
signal verify_snk_out : t_dp_siso := c_dp_siso_rdy;
signal verify_snk_in : t_dp_sosi;
signal verify_snk_in_data : std_logic_vector(g_data_w - 1 downto 0);
signal prev_verify_snk_in_data : std_logic_vector(g_data_w - 1 downto 0);
begin
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
mm_clk <= (not mm_clk) or tb_end after c_mm_clk_period / 2;
mm_rst <= '1', '0' after c_mm_clk_period * 7;
-- dp_clk <= (not dp_clk) or tb_end after c_dp_clk_period / 2;
ref_clk <= (not ref_clk) or tb_end after c_ref_clk_period / 2;
-- dp_rst <= '1', '0' after c_dp_clk_period * 7;
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity dp_lib.dp_stream_stimuli
generic map (
g_instance_nr => 0, -- only one stream so choose index 0
-- flow control
g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
g_pulse_active => c_stimuli_pulse_active,
g_pulse_period => c_stimuli_pulse_period,
g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
g_data_init => c_data_init,
g_bsn_init => c_bsn_init,
-- specific
g_in_dat_w => g_data_w,
g_nof_repeat => c_nof_packets,
g_pkt_len => g_pkt_len,
g_pkt_gap => g_pkt_gap,
g_wait_last_evt => c_wait_last_evt
)
port map (
rst => mm_rst,
clk => dp_clk,
-- Generate stimuli
src_in => stimuli_src_in,
src_out => stimuli_src_out,
-- End of stimuli
last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
);
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
-- Select fields that need to be verified
-- . during the test
verify_snk_in_enable.sync <= '0';
verify_snk_in_enable.bsn <= '0';
verify_snk_in_enable.data <= '1';
verify_snk_in_enable.re <= '0';
verify_snk_in_enable.im <= '0';
verify_snk_in_enable.valid <= '1';
verify_snk_in_enable.sop <= '1';
verify_snk_in_enable.eop <= '1';
verify_snk_in_enable.empty <= '1';
verify_snk_in_enable.channel <= '0';
verify_snk_in_enable.err <= '0';
-- . after the test
verify_last_snk_in_evt.sync <= '0';
verify_last_snk_in_evt.bsn <= '0'; -- thanks to using rx_hdr_fields_raw_arr for bsn field
verify_last_snk_in_evt.data <= last_snk_in_evt;
verify_last_snk_in_evt.re <= '0';
verify_last_snk_in_evt.im <= '0';
verify_last_snk_in_evt.valid <= last_snk_in_evt;
verify_last_snk_in_evt.sop <= last_snk_in_evt;
verify_last_snk_in_evt.eop <= last_snk_in_evt;
verify_last_snk_in_evt.empty <= last_snk_in_evt;
verify_last_snk_in_evt.channel <= '0';
verify_last_snk_in_evt.err <= '0';
u_dp_stream_verify : entity dp_lib.dp_stream_verify
generic map (
g_instance_nr => 0, -- only one stream so choose index 0
-- flow control
g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
g_pulse_active => c_verify_pulse_active,
g_pulse_period => c_verify_pulse_period,
g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
-- specific
g_in_dat_w => g_data_w,
g_pkt_len => c_expected_pkt_len
)
port map (
rst => mm_rst,
clk => dp_clk,
-- Verify data
snk_out => verify_snk_out,
snk_in => verify_snk_in,
-- During stimuli
verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-- End of stimuli
expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
);
------------------------------------------------------------------------------
-- DUT offload Tx
------------------------------------------------------------------------------
u_tx : entity work.tech_eth_200g
port map (
in_refclk_fgt => ref_clk,
in_refclk_fht => ref_clk,
reconfig_clk => mm_clk,
reconfig_rst => mm_rst,
ninit_done => mm_rst,
rst_n => open,
tx_rst_n => open,
rx_rst_n => open,
tx_serial => serial_loopback,
rx_serial => serial_loopback,
tx_serial_n => serial_loopback_n,
rx_serial_n => serial_loopback_n,
tx_sosi => stimuli_src_out,
tx_siso => stimuli_src_in,
rx_sosi => verify_snk_in,
out_dp_clk => dp_clk,
tx_pll_locked => tx_pll_locked
);
------------------------------------------------------------------------------
-- Auxiliary
------------------------------------------------------------------------------
-- Map to slv to ease monitoring in wave window
stimuli_src_out_data <= stimuli_src_out.data(g_data_w - 1 downto 0);
verify_snk_in_data <= verify_snk_in.data(g_data_w - 1 downto 0);
end tb;
--------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--------------------------------------------------------------------------------
-- Purpose:
-- Description:
--
library IEEE, common_lib, dp_lib, technology_lib;
use IEEE.std_logic_1164.all;
use technology_lib.technology_pkg.all;
use technology_lib.technology_select_pkg.all;
use common_lib.common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use work.tech_eth_200g_component_pkg.all;
entity tech_eth_200g is
generic (
g_technology : natural := c_tech_select_default
);
port (
in_refclk_fgt : in std_logic;
in_refclk_fht : in std_logic;
reconfig_clk : in std_logic := '1';
reconfig_rst : in std_logic := '0';
ninit_done : in std_logic := '1';
rst_n : in std_logic := '1';
tx_rst_n : in std_logic := '1';
rx_rst_n : in std_logic := '1';
tx_serial : out std_logic_vector(3 downto 0);
rx_serial : in std_logic_vector(3 downto 0);
tx_serial_n : out std_logic_vector(3 downto 0);
rx_serial_n : in std_logic_vector(3 downto 0);
tx_sosi : in t_dp_sosi;
tx_siso : out t_dp_siso := c_dp_siso_rdy;
rx_sosi : out t_dp_sosi;
out_dp_clk : out std_logic; -- 415.0390625 MHz
tx_pll_locked : out std_logic
);
end tech_eth_200g;
architecture str of tech_eth_200g is
begin
gen_ip_agi027_1e1v : if g_technology = c_tech_agi027_1e1v generate
u0 : entity work.tech_eth_200g_agi027_1e1v
port map (in_refclk_fgt, in_refclk_fht, reconfig_clk, reconfig_rst,
ninit_done, rst_n, tx_rst_n, rx_rst_n, tx_serial,
rx_serial, tx_serial_n, rx_serial_n, tx_sosi,
tx_siso, rx_sosi, out_dp_clk, tx_pll_locked);
end generate;
end str;
--------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--------------------------------------------------------------------------------
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
--library ip_agi027_1e1v_eth_200g;
--library ip_agi027_1e1v_eth_sysclk;
library IEEE, technology_lib, common_lib, dp_lib, tech_ip_agi027_1e1v_eth_200g_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use common_lib.common_interface_layers_pkg.all;
use dp_lib.dp_stream_pkg.all;
use technology_lib.technology_pkg.all;
use work.tech_eth_200g_component_pkg.all;
entity tech_eth_200g_agi027_1e1v is
port (
in_refclk_fgt : in std_logic;
in_refclk_fht : in std_logic;
reconfig_clk : in std_logic := '1';
reconfig_rst : in std_logic := '0';
ninit_done : in std_logic := '1';
rst_n : in std_logic := '1';
tx_rst_n : in std_logic := '1';
rx_rst_n : in std_logic := '1';
tx_serial : out std_logic_vector(3 downto 0);
rx_serial : in std_logic_vector(3 downto 0);
tx_serial_n : out std_logic_vector(3 downto 0);
rx_serial_n : in std_logic_vector(3 downto 0);
tx_sosi : in t_dp_sosi;
tx_siso : out t_dp_siso := c_dp_siso_rdy;
rx_sosi : out t_dp_sosi;
out_dp_clk : out std_logic; -- 415.0390625 MHz
tx_pll_locked : out std_logic
);
end tech_eth_200g_agi027_1e1v;
architecture str of tech_eth_200g_agi027_1e1v is
signal i_clk_sys : std_logic;
signal i_clk_ref : std_logic;
signal clk_pll : std_logic;
signal i_reconfig_rst : std_logic;
signal reconfig_rst_sync : std_logic;
signal tx_lanes_stable : std_logic;
signal tx_lanes_stable_sync : std_logic;
signal ninit_done_sync : std_logic;
signal reset_till_lanes_stable : std_logic;
signal i_tx_mac_data : std_logic_vector(511 downto 0) := (others => 'X');
signal i_tx_mac_valid : std_logic := '0';
signal i_tx_mac_inframe : std_logic_vector(7 downto 0) := (others => 'X');
signal i_tx_mac_eop_empty : std_logic_vector(23 downto 0) := (others => 'X');
signal o_tx_mac_ready : std_logic;
signal i_tx_mac_error : std_logic_vector(7 downto 0) := (others => 'X');
signal i_tx_mac_skip_crc : std_logic_vector(7 downto 0) := (others => 'X');
signal o_rx_mac_data : std_logic_vector(511 downto 0);
signal o_rx_mac_valid : std_logic;
signal o_rx_mac_inframe : std_logic_vector(7 downto 0);
signal o_rx_mac_eop_empty : std_logic_vector(23 downto 0);
signal o_rx_mac_fcs_error : std_logic_vector(7 downto 0);
signal o_rx_mac_error : std_logic_vector(15 downto 0);
signal o_rx_mac_status : std_logic_vector(23 downto 0);
type t_state is (s_wait_for_sop, s_wait_for_eop);
type t_tx_reg is record -- record to keep the registers organized.
state : t_state;
tx_mac_inframe : std_logic_vector(c_tech_eth_200g_nof_seg - 1 downto 0);
end record;
constant c_tx_reg_rst : t_tx_reg := (s_wait_for_sop, (others => '0'));
signal d_tx, q_tx : t_tx_reg;
type t_rx_reg is record -- record to keep the registers organized.
state : t_state;
p, sosi_sel : integer range 0 to 1;
i, j : integer range 0 to ( c_tech_eth_200g_nof_seg -1 );
rx_sosi : t_dp_sosi_arr(1 downto 0);
out_rx_sosi : t_dp_sosi;
end record;
constant c_rx_reg_rst : t_rx_reg := (s_wait_for_sop, 0, 0, 0, 0, (others => c_dp_sosi_rst), c_dp_sosi_rst);
signal d_rx, q_rx : t_rx_reg;
begin
u_common_areset : entity common_lib.common_areset
generic map (
g_rst_level => '1', -- power up default will be inferred in FPGA
g_delay_len => c_meta_delay_len
)
port map (
in_rst => reconfig_rst,
clk => reconfig_clk,
out_rst => reconfig_rst_sync
);
u_common_async_tx : entity common_lib.common_async
generic map (
g_rst_level => '1'
)
port map (
rst => '0',
clk => reconfig_clk,
din => tx_lanes_stable,
dout => tx_lanes_stable_sync
);
u_common_async_init : entity common_lib.common_async
generic map (
g_rst_level => '1'
)
port map (
rst => '0',
clk => reconfig_clk,
din => ninit_done,
dout => ninit_done_sync
);
p_rst : process (reconfig_clk)
begin
if rising_edge(reconfig_clk) then
if ninit_done_sync = '1' then
reset_till_lanes_stable <= '1';
elsif tx_lanes_stable_sync = '1' then
reset_till_lanes_stable <= '0';
end if;
end if;
end process;
i_reconfig_rst <= (reconfig_rst_sync or reset_till_lanes_stable);
u_ip_agi027_1e1v_eth_sysclk : entity tech_ip_agi027_1e1v_eth_200g_lib.tech_ip_agi027_1e1v_eth_sysclk
port map (
out_systempll_clk_0 => i_clk_sys,
in_refclk_fgt_0 => in_refclk_fgt,
in_refclk_fht_0 => in_refclk_fht,
out_fht_cmmpll_clk_0 => i_clk_ref
);
u_ip_agi027_1e1v_eth_200g : entity tech_ip_agi027_1e1v_eth_200g_lib.tech_ip_agi027_1e1v_eth_200g
port map (
i_clk_tx => clk_pll, -- i_tx_clk.clk
i_clk_rx => clk_pll, -- i_rx_clk.clk
o_clk_pll => clk_pll, -- o_clk_pll.clk
i_reconfig_clk => reconfig_clk, -- i_reconfig_clk.clk
i_reconfig_reset => i_reconfig_rst, -- i_reconfig_reset.reset
i_clk_ref => i_clk_ref, -- i_clk_ref.clk
i_clk_sys => i_clk_sys, -- i_clk_sys.clk
i_rst_n => rst_n, -- i_rst_n.reset_n
i_tx_rst_n => tx_rst_n, -- i_tx_rst_n.reset_n
i_rx_rst_n => rx_rst_n, -- i_rx_rst_n.reset_n
o_rst_ack_n => open, -- reset_status_ports.o_rst_ack_n
o_tx_rst_ack_n => open, -- .o_tx_rst_ack_n
o_rx_rst_ack_n => open, -- .o_rx_rst_ack_n
o_tx_serial => tx_serial, -- serial.o_tx_serial
i_rx_serial => rx_serial, -- .i_rx_serial
o_tx_serial_n => tx_serial_n, -- .o_tx_serial_n
i_rx_serial_n => rx_serial_n, -- .i_rx_serial_n
o_cdr_lock => open, -- clock_status_ports.o_cdr_lock
o_tx_pll_locked => tx_pll_locked, -- .o_tx_pll_locked
o_tx_lanes_stable => tx_lanes_stable, -- .o_tx_lanes_stable
o_rx_pcs_ready => open, -- .o_rx_pcs_ready
i_tx_mac_data => i_tx_mac_data, -- tx_mac_seg.i_tx_mac_data
i_tx_mac_valid => i_tx_mac_valid, -- .i_tx_mac_valid
i_tx_mac_inframe => i_tx_mac_inframe, -- .i_tx_mac_inframe
i_tx_mac_eop_empty => i_tx_mac_eop_empty, -- .i_tx_mac_eop_empty
o_tx_mac_ready => o_tx_mac_ready, -- .o_tx_mac_ready
i_tx_mac_error => i_tx_mac_error, -- .i_tx_mac_error
i_tx_mac_skip_crc => i_tx_mac_skip_crc, -- .i_tx_mac_skip_crc
o_rx_mac_data => o_rx_mac_data, -- rx_mac_seg.o_rx_mac_data
o_rx_mac_valid => o_rx_mac_valid, -- .o_rx_mac_valid
o_rx_mac_inframe => o_rx_mac_inframe, -- .o_rx_mac_inframe
o_rx_mac_eop_empty => o_rx_mac_eop_empty, -- .o_rx_mac_eop_empty
o_rx_mac_fcs_error => o_rx_mac_fcs_error, -- .o_rx_mac_fcs_error
o_rx_mac_error => o_rx_mac_error, -- .o_rx_mac_error
o_rx_mac_status => o_rx_mac_status, -- .o_rx_mac_status
i_clk_pll => '0' -- i_clk_pll.clk
);
---------------------------------------------
-- Translate TX sosi/siso to tx mac interface
---------------------------------------------
out_dp_clk <= clk_pll;
-- State machine to derive tx_mac_inframe.
q_tx <= d_tx when rising_edge(clk_pll);
p_tx_comb : process (q_tx, tx_sosi)
variable v : t_tx_reg;
begin
v := q_tx;
case q_tx.state is
when s_wait_for_sop =>
if tx_sosi.sop = '1' and tx_sosi.valid = '1' then
v.tx_mac_inframe := (others => '1');
v.state := s_wait_for_eop;
else
v.tx_mac_inframe := (others => '0');
end if;
when s_wait_for_eop => -- keep inframe at all '1' until eop.
if tx_sosi.eop = '1' and tx_sosi.valid = '1' then
v.tx_mac_inframe := func_tech_eth_200g_empty_to_inframe(tx_sosi.empty);
v.state := s_wait_for_sop;
end if;
end case;
d_tx <= v;
end process;
i_tx_mac_data <= func_tech_eth_200g_flip_symbols(tx_sosi.data(c_tech_eth_200g_data_w - 1 downto 0));
i_tx_mac_valid <= tx_sosi.valid;
i_tx_mac_inframe <= d_tx.tx_mac_inframe;
gen_empty : for i in 0 to c_tech_eth_200g_nof_seg - 1 generate
i_tx_mac_eop_empty( 3*(i+1) - 1 downto 3*i) <= tx_sosi.empty(2 downto 0);
end generate;
i_tx_mac_error <= (others => '0');
i_tx_mac_skip_crc <= (others => '0');
tx_siso.ready <= o_tx_mac_ready;
---------------------------------------------
-- Translate rx mac interface to RX Sosi
---------------------------------------------
-- State machine to derive sop/eop from rx_mac_inframe.
q_rx <= d_rx when rising_edge(clk_pll);
p_rx_comb : process (q_rx, o_rx_mac_inframe, o_rx_mac_data, o_rx_mac_valid, o_rx_mac_eop_empty, o_rx_mac_error)
variable v : t_rx_reg;
begin
v := q_rx;
v.sosi_sel := q_rx.p;
v.out_rx_sosi := q_rx.rx_sosi(q_rx.sosi_sel);
v.out_rx_sosi.data := RESIZE_DP_DATA(func_tech_eth_200g_flip_symbols(q_rx.rx_sosi(q_rx.sosi_sel).data(c_tech_eth_200g_data_w - 1 downto 0)));
v.rx_sosi(q_rx.p).valid := o_rx_mac_valid;
v.rx_sosi(q_rx.p).err := RESIZE_DP_ERROR(o_rx_mac_error);
case q_rx.state is
when s_wait_for_sop =>
if orv(o_rx_mac_inframe) = '1' and o_rx_mac_valid = '1' then -- must contain sop
v.rx_sosi(q_rx.p).sop := '1';
v.i := 0;
v.j := 0;
for i in 1 to c_tech_eth_200g_nof_seg - 1 loop
if o_rx_mac_inframe(i) = '1' and o_rx_mac_inframe(i-1) = '0' then -- Find sop segment
v.i := i;
end if;
if o_rx_mac_inframe(i) = '0' and o_rx_mac_inframe(i-1) = '1' then -- Find eop segment if there is one.
v.j := i;
end if;
end loop;
-- shift data to correct position basd on the segment index of the sop.
-- no need to clear bits if there is an eop, as these can simply be marked as empty.
v.rx_sosi(q_rx.p).data((c_tech_eth_200g_nof_seg - v.i) * c_tech_eth_200g_seg_w - 1 downto 0) := o_rx_mac_data(c_tech_eth_200g_data_w - 1 downto v.i * c_tech_eth_200g_seg_w);
if v.j > v.i then -- eop after sop in same frame.
v.rx_sosi(q_rx.p).eop := '1';
v.rx_sosi(q_rx.p).empty(c_tech_eth_200g_seg_empty_w - 1 downto 0) := o_rx_mac_eop_empty((v.j + 1) * c_tech_eth_200g_seg_empty_w - 1 downto v.j * c_tech_eth_200g_seg_empty_w);
v.rx_sosi(q_rx.p).empty(c_tech_eth_200g_empty_w - 1 downto c_tech_eth_200g_seg_empty_w) := not to_uvec(v.j, c_tech_eth_200g_empty_w - c_tech_eth_200g_seg_empty_w);
v.p := not_int(q_rx.p);
elsif v.i = 0 then
v.p := not_int(q_rx.p);
v.state := s_wait_for_eop;
else
v.state := s_wait_for_eop;
end if;
end if;
when s_wait_for_eop =>
-- handle data while waiting for eop.
if o_rx_mac_valid = '1' then
v.p := not_int(q_rx.p);
if q_rx.i = 0 then
v.rx_sosi(q_rx.p).data(c_tech_eth_200g_data_w - 1 downto 0) := o_rx_mac_data;
else
v.rx_sosi(q_rx.p).data(c_tech_eth_200g_data_w - 1 downto (c_tech_eth_200g_nof_seg - q_rx.i) * c_tech_eth_200g_seg_w) := o_rx_mac_data(q_rx.i * c_tech_eth_200g_seg_w - 1 downto 0);
v.rx_sosi(v.p).data((c_tech_eth_200g_nof_seg - q_rx.i) * c_tech_eth_200g_seg_w -1 downto 0) := o_rx_mac_data(c_tech_eth_200g_data_w - 1 downto v.i * c_tech_eth_200g_seg_w);
end if;
-- check if cycle contains eop.
if orv(not o_rx_mac_inframe) = '1' then -- must contain eop
v.i := 0;
v.j := 0;
for i in 1 to c_tech_eth_200g_nof_seg - 1 loop
if o_rx_mac_inframe(i) = '1' and o_rx_mac_inframe(i-1) = '0' then -- Find sop segment if there is one
v.i := i;
end if;
if o_rx_mac_inframe(i) = '0' and o_rx_mac_inframe(i-1) = '1' then -- Find eop segment.
v.j := i;
end if;
end loop;
if v.j < q_rx.i or q_rx.i = 0 then -- eop falls in current frame
v.rx_sosi(q_rx.p).eop := '1';
v.rx_sosi(q_rx.p).empty(c_tech_eth_200g_seg_empty_w - 1 downto 0) := o_rx_mac_eop_empty((v.j + 1) * c_tech_eth_200g_seg_empty_w - 1 downto v.j * c_tech_eth_200g_seg_empty_w);
v.rx_sosi(q_rx.p).empty(c_tech_eth_200g_empty_w - 1 downto c_tech_eth_200g_seg_empty_w) := not to_uvec(v.j, c_tech_eth_200g_empty_w - c_tech_eth_200g_seg_empty_w);
else -- eop falls in next frame
v.rx_sosi(v.p).eop := '1';
v.rx_sosi(v.p).empty(c_tech_eth_200g_seg_empty_w - 1 downto 0) := o_rx_mac_eop_empty;
v.rx_sosi(v.p).empty(c_tech_eth_200g_empty_w - 1 downto c_tech_eth_200g_seg_empty_w) := not to_uvec(v.j, c_tech_eth_200g_empty_w - c_tech_eth_200g_seg_empty_w);
end if;
if v.i > v.j then -- sop after eop in same frame, must fall in next frame
v.rx_sosi(v.p).sop := '1';
v.rx_sosi(v.p).data((c_tech_eth_200g_nof_seg - v.i) * c_tech_eth_200g_seg_w - 1 downto 0) := o_rx_mac_data(c_tech_eth_200g_data_w - 1 downto v.i * c_tech_eth_200g_seg_w);
else -- no sop, so wait for sop.
v.state := s_wait_for_sop;
end if;
end if;
end if;
end case;
d_rx <= v;
end process;
end str;
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: IP components declarations for various devices that get wrapped by the tech components
library IEEE, technology_lib, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use common_lib.common_interface_layers_pkg.all;
use technology_lib.technology_pkg.all;
use dp_lib.dp_stream_pkg.all;
package tech_eth_200g_component_pkg is
constant c_tech_eth_200g_nof_seg : natural := 8;
constant c_tech_eth_200g_data_w : natural := 512;
constant c_tech_eth_200g_seg_w : natural := ceil_div(c_tech_eth_200g_data_w, c_tech_eth_200g_nof_seg);
constant c_tech_eth_200g_symbol_w : natural := c_byte_w; -- = 8 bit
constant c_tech_eth_200g_symbols_per_beat : natural := ceil_div(c_tech_eth_200g_data_w, c_tech_eth_200g_symbol_w);
constant c_tech_eth_200g_symbols_per_seg : natural := ceil_div(c_tech_eth_200g_seg_w, c_tech_eth_200g_symbol_w);
constant c_tech_eth_200g_empty_w : natural := ceil_log2(c_tech_eth_200g_symbols_per_beat);
constant c_tech_eth_200g_seg_empty_w : natural := ceil_log2(c_tech_eth_200g_symbols_per_seg);
------------------------------------------------------------------------------
-- Agilex7
------------------------------------------------------------------------------
component ip_agi027_1e1v_eth_200g is
port (
i_clk_tx : in std_logic := 'X'; -- clk
i_clk_rx : in std_logic := 'X'; -- clk
o_clk_pll : out std_logic; -- clk
i_reconfig_clk : in std_logic := 'X'; -- clk
i_reconfig_reset : in std_logic := 'X'; -- reset
o_sys_pll_locked : out std_logic; -- o_sys_pll_locked
o_tx_serial : out std_logic_vector(3 downto 0); -- o_tx_serial
i_rx_serial : in std_logic_vector(3 downto 0) := (others => 'X'); -- i_rx_serial
o_tx_serial_n : out std_logic_vector(3 downto 0); -- o_tx_serial_n
i_rx_serial_n : in std_logic_vector(3 downto 0) := (others => 'X'); -- i_rx_serial_n
i_clk_ref : in std_logic := 'X'; -- clk
i_clk_sys : in std_logic := 'X'; -- clk
i_reconfig_eth_addr : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
i_reconfig_eth_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
o_reconfig_eth_readdata_valid : out std_logic; -- readdatavalid
i_reconfig_eth_read : in std_logic := 'X'; -- read
i_reconfig_eth_write : in std_logic := 'X'; -- write
o_reconfig_eth_readdata : out std_logic_vector(31 downto 0); -- readdata
i_reconfig_eth_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
o_reconfig_eth_waitrequest : out std_logic; -- waitrequest
i_rst_n : in std_logic := 'X'; -- reset_n
i_tx_rst_n : in std_logic := 'X'; -- reset_n
i_rx_rst_n : in std_logic := 'X'; -- reset_n
o_rst_ack_n : out std_logic; -- o_rst_ack_n
o_tx_rst_ack_n : out std_logic; -- o_tx_rst_ack_n
o_rx_rst_ack_n : out std_logic; -- o_rx_rst_ack_n
o_cdr_lock : out std_logic; -- o_cdr_lock
o_tx_pll_locked : out std_logic; -- o_tx_pll_locked
o_tx_lanes_stable : out std_logic; -- o_tx_lanes_stable
o_rx_pcs_ready : out std_logic; -- o_rx_pcs_ready
o_clk_tx_div : out std_logic; -- clk
o_clk_rec_div64 : out std_logic; -- clk
o_clk_rec_div : out std_logic; -- clk
o_rx_block_lock : out std_logic; -- o_rx_block_lock
o_rx_am_lock : out std_logic; -- o_rx_am_lock
o_local_fault_status : out std_logic; -- o_local_fault_status
o_remote_fault_status : out std_logic; -- o_remote_fault_status
i_stats_snapshot : in std_logic := 'X'; -- i_stats_snapshot
o_rx_hi_ber : out std_logic; -- o_rx_hi_ber
o_rx_pcs_fully_aligned : out std_logic; -- o_rx_pcs_fully_aligned
i_tx_mac_data : in std_logic_vector(511 downto 0) := (others => 'X'); -- i_tx_mac_data
i_tx_mac_valid : in std_logic := 'X'; -- i_tx_mac_valid
i_tx_mac_inframe : in std_logic_vector(7 downto 0) := (others => 'X'); -- i_tx_mac_inframe
i_tx_mac_eop_empty : in std_logic_vector(23 downto 0) := (others => 'X'); -- i_tx_mac_eop_empty
o_tx_mac_ready : out std_logic; -- o_tx_mac_ready
i_tx_mac_error : in std_logic_vector(7 downto 0) := (others => 'X'); -- i_tx_mac_error
i_tx_mac_skip_crc : in std_logic_vector(7 downto 0) := (others => 'X'); -- i_tx_mac_skip_crc
o_rx_mac_data : out std_logic_vector(511 downto 0); -- o_rx_mac_data
o_rx_mac_valid : out std_logic; -- o_rx_mac_valid
o_rx_mac_inframe : out std_logic_vector(7 downto 0); -- o_rx_mac_inframe
o_rx_mac_eop_empty : out std_logic_vector(23 downto 0); -- o_rx_mac_eop_empty
o_rx_mac_fcs_error : out std_logic_vector(7 downto 0); -- o_rx_mac_fcs_error
o_rx_mac_error : out std_logic_vector(15 downto 0); -- o_rx_mac_error
o_rx_mac_status : out std_logic_vector(23 downto 0); -- o_rx_mac_status
i_tx_pfc : in std_logic_vector(7 downto 0) := (others => 'X'); -- i_tx_pfc
o_rx_pfc : out std_logic_vector(7 downto 0); -- o_rx_pfc
i_tx_pause : in std_logic := 'X'; -- i_tx_pause
o_rx_pause : out std_logic; -- o_rx_pause
i_reconfig_xcvr0_addr : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
i_reconfig_xcvr0_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
o_reconfig_xcvr0_readdata_valid : out std_logic; -- readdatavalid
i_reconfig_xcvr0_read : in std_logic := 'X'; -- read
i_reconfig_xcvr0_write : in std_logic := 'X'; -- write
o_reconfig_xcvr0_readdata : out std_logic_vector(31 downto 0); -- readdata
i_reconfig_xcvr0_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
o_reconfig_xcvr0_waitrequest : out std_logic; -- waitrequest
i_reconfig_xcvr1_addr : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
i_reconfig_xcvr1_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
o_reconfig_xcvr1_readdata_valid : out std_logic; -- readdatavalid
i_reconfig_xcvr1_read : in std_logic := 'X'; -- read
i_reconfig_xcvr1_write : in std_logic := 'X'; -- write
o_reconfig_xcvr1_readdata : out std_logic_vector(31 downto 0); -- readdata
i_reconfig_xcvr1_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
o_reconfig_xcvr1_waitrequest : out std_logic; -- waitrequest
i_reconfig_xcvr2_addr : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
i_reconfig_xcvr2_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
o_reconfig_xcvr2_readdata_valid : out std_logic; -- readdatavalid
i_reconfig_xcvr2_read : in std_logic := 'X'; -- read
i_reconfig_xcvr2_write : in std_logic := 'X'; -- write
o_reconfig_xcvr2_readdata : out std_logic_vector(31 downto 0); -- readdata
i_reconfig_xcvr2_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
o_reconfig_xcvr2_waitrequest : out std_logic; -- waitrequest
i_reconfig_xcvr3_addr : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
i_reconfig_xcvr3_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
o_reconfig_xcvr3_readdata_valid : out std_logic; -- readdatavalid
i_reconfig_xcvr3_read : in std_logic := 'X'; -- read
i_reconfig_xcvr3_write : in std_logic := 'X'; -- write
o_reconfig_xcvr3_readdata : out std_logic_vector(31 downto 0); -- readdata
i_reconfig_xcvr3_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
o_reconfig_xcvr3_waitrequest : out std_logic; -- waitrequest
i_clk_pll : in std_logic := 'X' -- clk
);
end component ip_agi027_1e1v_eth_200g;
component ip_agi027_1e1v_eth_sysclk is
port (
out_systempll_synthlock_0 : out std_logic; -- out_systempll_synthlock
out_systempll_clk_0 : out std_logic; -- clk
in_refclk_fgt_0 : in std_logic := 'X'; -- in_refclk_fgt_0
in_refclk_fht_0 : in std_logic := 'X'; -- in_refclk_fht_0
out_fht_cmmpll_clk_0 : out std_logic -- clk
);
end component ip_agi027_1e1v_eth_sysclk;
function func_tech_eth_200g_flip_symbols(data : std_logic_vector(c_tech_eth_200g_data_w - 1 downto 0)) return std_logic_vector;
function func_tech_eth_200g_empty_to_inframe(empty : std_logic_vector(c_dp_stream_empty_w - 1 downto 0)) return std_logic_vector;
end tech_eth_200g_component_pkg;
package body tech_eth_200g_component_pkg is
function func_tech_eth_200g_flip_symbols(data : std_logic_vector(c_tech_eth_200g_data_w - 1 downto 0)) return std_logic_vector is
variable v_out_data : std_logic_vector(c_tech_eth_200g_data_w - 1 downto 0);
constant c_sym_w : natural := c_tech_eth_200g_symbol_w;
constant c_nof_sym : natural := c_tech_eth_200g_symbols_per_beat;
begin
for I in 0 to c_nof_sym - 1 loop
v_out_data( (I + 1) * c_sym_w - 1 downto I * c_sym_w) := data((c_nof_sym - I) * c_sym_w - 1 downto (c_nof_sym - 1 - I) * c_sym_w);
end loop;
return v_out_data;
end func_tech_eth_200g_flip_symbols;
function func_tech_eth_200g_empty_to_inframe(empty : std_logic_vector(c_dp_stream_empty_w - 1 downto 0)) return std_logic_vector is
variable v_inframe : std_logic_vector(c_tech_eth_200g_nof_seg - 1 downto 0) := (others => '0');
variable v_seg_id : natural := 0;
begin
v_seg_id := to_uint(not empty(c_tech_eth_200g_empty_w - 1 downto 3));
for i in 0 to c_tech_eth_200g_nof_seg - 1 loop
if v_seg_id <= i then
v_inframe(i) := '1';
end if;
end loop;
return v_inframe;
end func_tech_eth_200g_empty_to_inframe;
end tech_eth_200g_component_pkg;
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#set ORIGIN "$env(PWD)"
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate"
# ETH IP
# Set QSYS_SIMDIR for msim_setup.tcl
set FORCE_MODELSIM_AE_SELECTION "true"
set QSYS_SIMDIR "$IP_DIR/ip_agi027_1e1v_eth_200g/sim/"
source "$IP_DIR/ip_agi027_1e1v_eth_200g/sim/mentor/msim_setup.tcl"
# Comile IP using msim_setup command "com"
com
vmap work ./work/
vcom "$IP_DIR/ip_agi027_1e1v_eth_200g/sim/ip_agi027_1e1v_eth_200g.vhd"
# Sys Clock IP
set QSYS_SIMDIR "$IP_DIR/ip_agi027_1e1v_eth_sysclk/sim/"
source "$IP_DIR/ip_agi027_1e1v_eth_sysclk/sim/mentor/msim_setup.tcl"
com
vmap work ./work/
vcom "$IP_DIR/ip_agi027_1e1v_eth_sysclk/sim/ip_agi027_1e1v_eth_sysclk.vhd"
hdl_lib_name = tech_ip_agi027_1e1v_eth_200g
hdl_library_clause_name = tech_ip_agi027_1e1v_eth_200g_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_uses_ip =
hdl_lib_technology = ip_agi027_1e1v
hdl_lib_disclose_library_clause_names =
# ip_agi027_1e1v_eth_200g ip_agi027_1e1v_eth_200g_lib
# ip_agi027_1e1v_eth_sysclk ip_agi027_1e1v_eth_sysclk_lib
synth_files =
tech_ip_agi027_1e1v_eth_200g.vhd
tech_ip_agi027_1e1v_eth_sysclk.vhd
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
#$HDL_BUILD_DIR/sim/ip_agi027_1e1v_eth_200g_tb.vhd
[modelsim_project_file]
modelsim_compile_ip_files =
$HDL_WORK/libraries/technology/ip_agi027_1e1v/eth_200g/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
$HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_1e1v_eth_200g/ip_agi027_1e1v_eth_200g.qip
$HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_1e1v_eth_sysclk/ip_agi027_1e1v_eth_sysclk.qip
[generate_ip_libs]
qsys-generate_ip_files =
ip_agi027_1e1v_eth_sysclk.ip
ip_agi027_1e1v_eth_200g.ip
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--------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--------------------------------------------------------------------------------
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
library IEEE;
use IEEE.std_logic_1164.all;
entity tech_ip_agi027_1e1v_eth_sysclk is
port (
out_systempll_synthlock_0 : out std_logic; -- out_systempll_synthlock
out_systempll_clk_0 : out std_logic; -- clk
in_refclk_fgt_0 : in std_logic := 'X'; -- in_refclk_fgt_0
in_refclk_fht_0 : in std_logic := 'X'; -- in_refclk_fht_0
out_fht_cmmpll_clk_0 : out std_logic -- clk
);
end tech_ip_agi027_1e1v_eth_sysclk;
architecture str of tech_ip_agi027_1e1v_eth_sysclk is
component ip_agi027_1e1v_eth_sysclk is
port (
out_systempll_synthlock_0 : out std_logic; -- out_systempll_synthlock
out_systempll_clk_0 : out std_logic; -- clk
in_refclk_fgt_0 : in std_logic := 'X'; -- in_refclk_fgt_0
in_refclk_fht_0 : in std_logic := 'X'; -- in_refclk_fht_0
out_fht_cmmpll_clk_0 : out std_logic -- clk
);
end component ip_agi027_1e1v_eth_sysclk;
begin
u_ip_agi027_1e1v_eth_sysclk : ip_agi027_1e1v_eth_sysclk
port map (
out_systempll_synthlock_0 => out_systempll_synthlock_0,
out_systempll_clk_0 => out_systempll_clk_0,
in_refclk_fgt_0 => in_refclk_fgt_0,
in_refclk_fht_0 => in_refclk_fht_0,
out_fht_cmmpll_clk_0 => out_fht_cmmpll_clk_0
);
end str;
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