-Added common_pulse_delay skeleton file.

libraries/base/common/hdllib.cfg

@@ -57,10 +57,11 @@ synth_files =
     src/vhdl/common_toggle.vhd
     src/vhdl/common_switch.vhd
     src/vhdl/common_request.vhd
-    src/vhdl/common_pulse_extend.vhd
-    src/vhdl/common_spulse.vhd
     src/vhdl/common_counter.vhd
     src/vhdl/common_init.vhd
+    src/vhdl/common_spulse.vhd
+    src/vhdl/common_pulse_extend.vhd
+    src/vhdl/common_pulse_delay.vhd
     src/vhdl/common_pulser.vhd
     src/vhdl/common_pulser_us_ms_s.vhd
     src/vhdl/common_led_controller.vhd

libraries/base/common/src/vhdl/common_pulse_delay.vhd

+--------------------------------------------------------------------------------
+--   Copyright (C) 2017
+--   ASTRON (Netherlands Institute for Radio Astronomy)
+--   P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+--   This file is part of the UniBoard software suite.
+--   The file is free software: you can redistribute it and/or modify
+--   it under the terms of the GNU General Public License as published by
+--   the Free Software Foundation, either version 3 of the License, or
+--   (at your option) any later version.
+--
+--   This program is distributed in the hope that it will be useful,
+--   but WITHOUT ANY WARRANTY; without even the implied warranty of
+--   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--   GNU General Public License for more details.
+--
+--   You should have received a copy of the GNU General Public License
+--   along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--------------------------------------------------------------------------------
+
+-- Author:
+-- . Daniel van der Schuur
+-- Purpose:
+-- . Produce pulse_out pulse_delay clk cycles after pulse_in
+-- Description:
+-- . 
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY common_pulse_delay IS
+  PORT (
+    clk         : IN  STD_LOGIC;
+    rst         : IN  STD_LOGIC;
+    pulse_in    : IN  STD_LOGIC;
+    pulse_delay : IN  STD_LOGIC;
+    pulse_out   : OUT STD_LOGIC
+  );
+END ENTITY common_pulse_delay;
+
+ARCHITECTURE rtl OF common_pulse_delay IS
+
+
+BEGIN
+
+
+
+END rtl;