Skip to content
Snippets Groups Projects
Commit efe767dc authored by Reinier van der Walle's avatar Reinier van der Walle
Browse files

added missing IP to hdllib

parent 552554f4
No related branches found
No related tags found
1 merge request!197Verified xsub with ring in simulation.
Pipeline #24640 passed
Stage: simulation
Stage: synthesis
Hide whitespace changes
Inline Side-by-side
applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg
+ 2
− 2
View file @ efe767dc
...@@ -7,10 +7,10 @@ hdl_lib_include_ip = ...@@ -7,10 +7,10 @@ hdl_lib_include_ip =
ip_arria10_e1sg_mac_10g ip_arria10_e1sg_mac_10g
ip_arria10_e1sg_pll_xgmii_mac_clocks ip_arria10_e1sg_pll_xgmii_mac_clocks
ip_arria10_e1sg_transceiver_pll_10g ip_arria10_e1sg_transceiver_pll_10g
ip_arria10_e1sg_phy_10gbase_r ip_arria10_e1sg_phy_10gbase_r
ip_arria10_e1sg_phy_10gbase_r_3
ip_arria10_e1sg_transceiver_reset_controller_1 ip_arria10_e1sg_transceiver_reset_controller_1
ip_arria10_e1sg_transceiver_reset_controller_3
synth_files = synth_files =
src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment