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Commit efbde822 authored by Pepping's avatar Pepping
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Fixed TO_SIGNED warning.

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libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd
+ 78
− 79
View file @ efbde822
...@@ -21,16 +21,12 @@ ...@@ -21,16 +21,12 @@
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- --
-- Purpose: Testbench for the fringe_stop_unit. -- Purpose: Testbench for the fringe_stop_unit.
-- To be used in conjunction with python testscript: ../python/tc_fringe_stop_unit.py
-- --
-- --
-- Usage -- Usage
-- > as 8 -- > as 8
-- > run 500 ns -- > run -all
-- > run python script in separate terminal: "python tc_fringe_stop_unit.py --unb 0 --fn 0 --sim" -- > Testbench is self-checking
-- > run 20 us or run -all
-- > Check the results of the python script.
-- > Stop the simulation manually in Modelsim by pressing the stop-button.
-- > Evalute the WAVE window. -- > Evalute the WAVE window.
LIBRARY IEEE, common_lib, technology_lib, mm_lib, diag_lib, dp_lib; LIBRARY IEEE, common_lib, technology_lib, mm_lib, diag_lib, dp_lib;
...@@ -51,14 +47,13 @@ USE work.fringe_stop_pkg.ALL; ...@@ -51,14 +47,13 @@ USE work.fringe_stop_pkg.ALL;
ENTITY tb_fringe_stop_unit IS ENTITY tb_fringe_stop_unit IS
GENERIC( GENERIC(
g_sim_type : NATURAL := 2; -- 0 = Increment, 1 = Increment over the maximum, 2 = Decrease, 3 = Decrease over the minimum
g_in_dat_w : POSITIVE := 8; -- Width of the incoming data. g_in_dat_w : POSITIVE := 8; -- Width of the incoming data.
g_fs_offset_w : POSITIVE := 10; -- Width of the offset of the linear coefficient g_fs_offset_w : POSITIVE := 10; -- Width of the offset of the linear coefficient
g_accu_w : POSITIVE := 31; -- Width of the accumulation register g_accu_w : POSITIVE := 31; -- Width of the accumulation register
g_fs_step_w : POSITIVE := 17; -- Width of the step of the linear coefficient g_fs_step_w : POSITIVE := 17; -- Width of the step of the linear coefficient
g_nof_channels : POSITIVE := 4; -- Number of serial channels for which the fringe stopping must be applied uniquely g_nof_channels : POSITIVE := 4; -- Number of serial channels for which the fringe stopping must be applied uniquely
g_phasor_w : POSITIVE := 9; -- Width of the phasor values in the lookup table g_phasor_w : POSITIVE := 9 -- Width of the phasor values in the lookup table
g_bf_weights_file_name : STRING := "../../../src/hex/weights"; -- "UNUSED" or relative path to e.g. the bf/build/data/weights hex file for adr_w=8 and dat_w=32
g_ss_wide_file_prefix : STRING := "../../../src/hex/ss_wide" -- path_to_file
); );
END tb_fringe_stop_unit; END tb_fringe_stop_unit;
...@@ -82,6 +77,8 @@ ARCHITECTURE tb OF tb_fringe_stop_unit IS ...@@ -82,6 +77,8 @@ ARCHITECTURE tb OF tb_fringe_stop_unit IS
SIGNAL dp_rst : STD_LOGIC; SIGNAL dp_rst : STD_LOGIC;
SIGNAL dp_clk : STD_LOGIC := '0'; SIGNAL dp_clk : STD_LOGIC := '0';
SIGNAL tb_end : STD_LOGIC := '0';
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- MM buses -- MM buses
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
...@@ -92,18 +89,6 @@ ARCHITECTURE tb OF tb_fringe_stop_unit IS ...@@ -92,18 +89,6 @@ ARCHITECTURE tb OF tb_fringe_stop_unit IS
SIGNAL ram_diag_bg_mosi : t_mem_mosi; SIGNAL ram_diag_bg_mosi : t_mem_mosi;
SIGNAL ram_diag_bg_miso : t_mem_miso; SIGNAL ram_diag_bg_miso : t_mem_miso;
SIGNAL ram_diag_data_buf_re_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_re_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_re_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_re_miso : t_mem_miso;
SIGNAL ram_diag_data_buf_im_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_im_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_im_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_im_miso : t_mem_miso;
-- DUT -- DUT
SIGNAL ram_fringe_stop_offset_mosi : t_mem_mosi := c_mem_mosi_rst; SIGNAL ram_fringe_stop_offset_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL ram_fringe_stop_offset_miso : t_mem_miso := c_mem_miso_rst; SIGNAL ram_fringe_stop_offset_miso : t_mem_miso := c_mem_miso_rst;
...@@ -127,8 +112,6 @@ ARCHITECTURE tb OF tb_fringe_stop_unit IS ...@@ -127,8 +112,6 @@ ARCHITECTURE tb OF tb_fringe_stop_unit IS
); );
END COMPONENT; END COMPONENT;
-- Custom definitions of constants
-- Configuration of the block generator: -- Configuration of the block generator:
CONSTANT c_bg_nof_output_streams : POSITIVE := 1; CONSTANT c_bg_nof_output_streams : POSITIVE := 1;
CONSTANT c_bg_buf_dat_w : POSITIVE := c_nof_complex*g_in_dat_w; CONSTANT c_bg_buf_dat_w : POSITIVE := c_nof_complex*g_in_dat_w;
...@@ -138,7 +121,7 @@ ARCHITECTURE tb OF tb_fringe_stop_unit IS ...@@ -138,7 +121,7 @@ ARCHITECTURE tb OF tb_fringe_stop_unit IS
CONSTANT c_block_size : NATURAL := g_nof_channels; CONSTANT c_block_size : NATURAL := g_nof_channels;
CONSTANT c_bg_gapsize : NATURAL := 0; CONSTANT c_bg_gapsize : NATURAL := 0;
CONSTANT c_bg_nof_blocks_per_sync : NATURAL := 64; CONSTANT c_bg_nof_blocks_per_sync : NATURAL := 128;
CONSTANT c_bg_mem_high_addr : NATURAL := g_nof_channels-1; CONSTANT c_bg_mem_high_addr : NATURAL := g_nof_channels-1;
...@@ -167,15 +150,13 @@ ARCHITECTURE tb OF tb_fringe_stop_unit IS ...@@ -167,15 +150,13 @@ ARCHITECTURE tb OF tb_fringe_stop_unit IS
SIGNAL fs_offset_matrix : t_integer_matrix(c_nof_sync_periods-1 DOWNTO 0, g_nof_channels-1 DOWNTO 0); SIGNAL fs_offset_matrix : t_integer_matrix(c_nof_sync_periods-1 DOWNTO 0, g_nof_channels-1 DOWNTO 0);
SIGNAL fs_step_matrix : t_integer_matrix(c_nof_sync_periods-1 DOWNTO 0, g_nof_channels-1 DOWNTO 0); SIGNAL fs_step_matrix : t_integer_matrix(c_nof_sync_periods-1 DOWNTO 0, g_nof_channels-1 DOWNTO 0);
SIGNAL re_error : INTEGER := 0;
SIGNAL im_error : INTEGER := 0;
TYPE reg_type IS RECORD TYPE reg_type IS RECORD
out_sosi_arr : t_dp_sosi_arr(1 DOWNTO 0); out_sosi_arr : t_dp_sosi_arr(1 DOWNTO 0);
accu_reg : t_integer_arr(g_nof_channels-1 DOWNTO 0); accu_reg : t_integer_arr(g_nof_channels-1 DOWNTO 0);
chn_cnt : INTEGER; chn_cnt : INTEGER;
sop_cnt : INTEGER; sop_cnt : INTEGER;
sync_cnt : INTEGER; sync_cnt : INTEGER;
loop_cnt : INTEGER;
step : INTEGER; step : INTEGER;
first_chn : BOOLEAN; first_chn : BOOLEAN;
first_sop : BOOLEAN; first_sop : BOOLEAN;
...@@ -185,7 +166,7 @@ ARCHITECTURE tb OF tb_fringe_stop_unit IS ...@@ -185,7 +166,7 @@ ARCHITECTURE tb OF tb_fringe_stop_unit IS
ref_im : INTEGER; ref_im : INTEGER;
END RECORD; END RECORD;
CONSTANT c_reg_type_rst : reg_type := ((OTHERS => c_dp_sosi_rst), (OTHERS => 0), 0, 0, 0, 0, TRUE, TRUE, TRUE, 0, 0, 0) ; CONSTANT c_reg_type_rst : reg_type := ((OTHERS => c_dp_sosi_rst), (OTHERS => 0), 0, 0, 0, 0, 0, TRUE, TRUE, TRUE, 0, 0, 0) ;
SIGNAL r : reg_type := c_reg_type_rst; SIGNAL r : reg_type := c_reg_type_rst;
SIGNAL rin : reg_type := c_reg_type_rst; SIGNAL rin : reg_type := c_reg_type_rst;
...@@ -195,10 +176,10 @@ BEGIN ...@@ -195,10 +176,10 @@ BEGIN
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Clock and reset generation -- Clock and reset generation
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
mm_clk <= NOT mm_clk AFTER c_mm_clk_period/2; mm_clk <= (NOT mm_clk) OR tb_end AFTER c_mm_clk_period/2;
mm_rst <= '1', '0' AFTER c_mm_clk_period*5; mm_rst <= '1', '0' AFTER c_mm_clk_period*5;
dp_clk <= NOT dp_clk AFTER c_dp_clk_period/2; dp_clk <= (NOT dp_clk) OR tb_end AFTER c_dp_clk_period/2;
dp_rst <= '1', '0' AFTER c_dp_clk_period*5; dp_rst <= '1', '0' AFTER c_dp_clk_period*5;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
...@@ -206,29 +187,6 @@ BEGIN ...@@ -206,29 +187,6 @@ BEGIN
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps); proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
----------------------------------------------------------------------------
-- MM buses
----------------------------------------------------------------------------
-- TB
-- u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_BG")
-- PORT MAP(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
-- u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_BG")
-- PORT MAP(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
-- DUT
-- u_mm_file_ram_fringe_stop_offset : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_FRINGE_STOP_OFFSET")
-- PORT MAP(mm_rst, mm_clk, ram_fringe_stop_offset_mosi, ram_fringe_stop_offset_miso);
-- u_mm_file_ram_fringe_stop_step : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_FRINGE_STOP_STEP")
-- PORT MAP(mm_rst, mm_clk, ram_fringe_stop_step_mosi, ram_fringe_stop_step_miso);
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Stimuli: Create the stimuli values and calculate the reference array -- Stimuli: Create the stimuli values and calculate the reference array
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
...@@ -239,14 +197,45 @@ BEGIN ...@@ -239,14 +197,45 @@ BEGIN
VARIABLE v_ref_re : t_integer_matrix(c_bg_nof_blocks_per_sync-1 DOWNTO 0, g_nof_channels-1 DOWNTO 0); VARIABLE v_ref_re : t_integer_matrix(c_bg_nof_blocks_per_sync-1 DOWNTO 0, g_nof_channels-1 DOWNTO 0);
VARIABLE v_ref_im : t_integer_matrix(c_bg_nof_blocks_per_sync-1 DOWNTO 0, g_nof_channels-1 DOWNTO 0); VARIABLE v_ref_im : t_integer_matrix(c_bg_nof_blocks_per_sync-1 DOWNTO 0, g_nof_channels-1 DOWNTO 0);
BEGIN BEGIN
-- Init the values for the BG.
FOR J IN 0 TO g_nof_channels-1 LOOP
bg_data_arr_re(J) <= -1*g_nof_channels/2+J;
bg_data_arr_im(J) <= g_nof_channels/2-J;
END LOOP;
-- init fs_offset_matrix -- init fs_offset_matrix
FOR I IN 0 TO c_nof_sync_periods-1 LOOP FOR I IN 0 TO c_nof_sync_periods-1 LOOP
-- Normal increment, both offset and step.
IF g_sim_type = 0 THEN
FOR J IN 0 TO g_nof_channels-1 LOOP FOR J IN 0 TO g_nof_channels-1 LOOP
fs_offset_matrix(I,J) <= I+10+J; fs_offset_matrix(I,J) <= I+10+J;
fs_step_matrix(I,J) <= 2**16-1-g_nof_channels+J; fs_step_matrix(I,J) <= 2**(g_fs_step_w-1)-1-g_nof_channels+J;
bg_data_arr_re(J) <= -1*g_nof_channels/2+J; END LOOP;
bg_data_arr_im(J) <= g_nof_channels/2-J; END IF;
-- Increment where sum reaches maximum and wraps.
IF g_sim_type = 1 THEN
FOR J IN 0 TO g_nof_channels-1 LOOP
fs_offset_matrix(I,J) <= 2**g_fs_offset_w-1;
fs_step_matrix(I,J) <= 2**(g_fs_step_w-1)-1-g_nof_channels+J;
END LOOP;
END IF;
-- Decrease the step and offset
IF g_sim_type = 2 THEN
FOR J IN 0 TO g_nof_channels-1 LOOP
fs_offset_matrix(I,J) <= 2**(g_fs_offset_w/2)+J-I;
fs_step_matrix(I,J) <= -1*2**(g_fs_step_w-1)+J;
END LOOP; END LOOP;
END IF;
-- Decrease where sum reaches minimum and wraps
IF g_sim_type = 3 THEN
FOR J IN 0 TO g_nof_channels-1 LOOP
fs_offset_matrix(I,J) <= 1;
fs_step_matrix(I,J) <= -1*2**(g_fs_step_w-1);
END LOOP;
END IF;
END LOOP; END LOOP;
WAIT; WAIT;
END PROCESS; END PROCESS;
...@@ -370,8 +359,10 @@ BEGIN ...@@ -370,8 +359,10 @@ BEGIN
out_sosi => out_sosi_arr(0) out_sosi => out_sosi_arr(0)
); );
p_verify_comb : PROCESS(r, dp_rst, out_sosi_arr, fs_offset_matrix, fs_step_matrix, bg_data_arr_re, bg_data_arr_im) p_reference_comb : PROCESS(r, dp_rst, out_sosi_arr, fs_offset_matrix, fs_step_matrix, bg_data_arr_re, bg_data_arr_im)
VARIABLE v : reg_type; VARIABLE v : reg_type;
VARIABLE v_sum_int : INTEGER;
VARIABLE v_sum_vec : STD_LOGIC_VECTOR(c_integer_w-1 DOWNTO 0);
BEGIN BEGIN
v := r; v := r;
v.out_sosi_arr(0) := out_sosi_arr(0); v.out_sosi_arr(0) := out_sosi_arr(0);
...@@ -402,6 +393,7 @@ BEGIN ...@@ -402,6 +393,7 @@ BEGIN
ELSE ELSE
IF r.sync_cnt = c_nof_sync_periods-1 THEN IF r.sync_cnt = c_nof_sync_periods-1 THEN
v.sync_cnt := 0; v.sync_cnt := 0;
v.loop_cnt := r.loop_cnt + 1;
ELSE ELSE
v.sync_cnt := r.sync_cnt + 1; v.sync_cnt := r.sync_cnt + 1;
END IF; END IF;
...@@ -411,43 +403,50 @@ BEGIN ...@@ -411,43 +403,50 @@ BEGIN
IF out_sosi_arr(0).valid = '1' THEN IF out_sosi_arr(0).valid = '1' THEN
IF v.sop_cnt = 0 THEN IF v.sop_cnt = 0 THEN
-- Flush the accumulation registers
FOR J IN 0 TO g_nof_channels-1 LOOP FOR J IN 0 TO g_nof_channels-1 LOOP
v.accu_reg(J) := fs_step_matrix(r.sync_cnt, J); v.accu_reg(J) := fs_step_matrix(r.sync_cnt, J);
END LOOP; END LOOP;
ELSE ELSE
-- Accumulate
v.accu_reg(v.chn_cnt) := r.accu_reg(v.chn_cnt) + fs_step_matrix(r.sync_cnt, v.chn_cnt); v.accu_reg(v.chn_cnt) := r.accu_reg(v.chn_cnt) + fs_step_matrix(r.sync_cnt, v.chn_cnt);
END IF; END IF;
-- Calculate the next reference value.
v.step := TO_UINT(TO_SVEC(v.accu_reg(v.chn_cnt), g_accu_w)(g_accu_w-1 DOWNTO g_accu_w - g_fs_offset_w)); v.step := TO_SINT(TO_SVEC(v.accu_reg(v.chn_cnt), g_accu_w)(g_accu_w-1 DOWNTO g_accu_w - g_fs_offset_w));
v.index := fs_offset_matrix(v.sync_cnt, v.chn_cnt) + v.step; v_sum_int := fs_offset_matrix(v.sync_cnt, v.chn_cnt) + v.step;
v_sum_vec := TO_SVEC(v_sum_int, c_integer_w);
v.index := TO_UINT(v_sum_vec(g_fs_offset_w-1 DOWNTO 0));
-- v.index := TO_UINT(TO_UVEC(temp, g_fs_offset_w+1)(g_fs_offset_w-1 DOWNTO 0));
-- v.index := TO_UINT(TO_UVEC(fs_offset_matrix(v.sync_cnt, v.chn_cnt) + v.step, g_fs_offset_w+1)(g_fs_offset_w-1 DOWNTO 0));
v.ref_re := COMPLEX_MULT_REAL( bg_data_arr_re(v.chn_cnt), bg_data_arr_im(v.chn_cnt), c_lookup_real(v.index), c_lookup_imag(v.index)); v.ref_re := COMPLEX_MULT_REAL( bg_data_arr_re(v.chn_cnt), bg_data_arr_im(v.chn_cnt), c_lookup_real(v.index), c_lookup_imag(v.index));
v.ref_im := COMPLEX_MULT_IMAG( bg_data_arr_re(v.chn_cnt), bg_data_arr_im(v.chn_cnt), c_lookup_real(v.index), c_lookup_imag(v.index)); v.ref_im := COMPLEX_MULT_IMAG( bg_data_arr_re(v.chn_cnt), bg_data_arr_im(v.chn_cnt), c_lookup_real(v.index), c_lookup_imag(v.index));
END IF; END IF;
rin <= v; rin <= v;
END PROCESS p_verify_comb; END PROCESS p_reference_comb;
regs : PROCESS(dp_clk) regs : PROCESS(dp_clk)
BEGIN BEGIN
IF rising_edge(dp_clk) THEN IF dp_rst = '1' THEN
r <= c_reg_type_rst;
ELSIF rising_edge(dp_clk) THEN
r <= rin; r <= rin;
END IF; END IF;
END PROCESS; END PROCESS;
p_verify2 : PROCESS(r.ref_re, r.ref_im, dp_clk, r.out_sosi_arr) p_verify : PROCESS(r.ref_re, r.ref_im, dp_clk, r.out_sosi_arr)
BEGIN BEGIN
IF rising_edge(dp_clk) THEN IF rising_edge(dp_clk) THEN
IF r.out_sosi_arr(0).valid = '1' THEN IF r.out_sosi_arr(0).valid = '1' THEN
IF r.ref_re /= TO_SINT(r.out_sosi_arr(0).re) THEN ASSERT TO_SINT(r.out_sosi_arr(0).re) = r.ref_re REPORT "Error: wrong result in real part DUT" SEVERITY ERROR;
re_error <= re_error + 1; ASSERT TO_SINT(r.out_sosi_arr(0).im) = r.ref_im REPORT "Error: wrong result in imaginary part DUT" SEVERITY ERROR;
END IF;
IF r.ref_im /= TO_SINT(r.out_sosi_arr(0).im) THEN
im_error <= im_error + 1;
END IF;
END IF; END IF;
END IF; END IF;
END PROCESS; END PROCESS;
tb_end <= '1' WHEN r.loop_cnt = 4 ELSE '0';
END tb; END tb;
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