Added sdp station image for unb2b. Also had to update the top-level to

align with the design for unb2c

applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd

@@ -96,7 +96,7 @@ END lofar2_unb2b_sdp_station_full;
 ARCHITECTURE str OF lofar2_unb2b_sdp_station_full IS
 
   SIGNAL JESD204B_SERIAL_DATA       : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1  downto 0);
-  SIGNAL jesd204b_sync_n_arr        : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1  downto 0);
+  SIGNAL jesd204b_sync_n_arr        : STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1  downto 0);
   SIGNAL JESD204B_REFCLK            : STD_LOGIC;
 
 

applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd

@@ -102,7 +102,7 @@ ENTITY lofar2_unb2b_sdp_station IS
  
     -- jesd204b syncronization signals
     JESD204B_SYSREF            : IN    STD_LOGIC;
-    JESD204B_SYNC_N            : OUT   STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0)
+    JESD204B_SYNC_N            : OUT   STD_LOGIC_VECTOR(c_sdp_N_sync_jesd-1 DOWNTO 0)
   );
 END lofar2_unb2b_sdp_station;
 

applications/lofar2/images/images.txt

@@ -10,3 +10,4 @@ lofar2_unb2b_sdp_station_bf-r087d98be6              | 2021-06-14    | R vd Walle
 lofar2_unb2b_sdp_station_xsub_one-r087d98be6        | 2021-06-14    | R vd Walle           | 
 unb2b_minimal-rce6b96eed                            | 2021-08-26    | P. Donker            | unb2b_minimal with new mmap, rbf maid with option --unb2_factory
 lofar2_unb2c_sdp_station_full-rbd06c78bb            | 2021-11-11    | R vd Walle           | Lofar2 SDP station full design for UniBoard2c.
+lofar2_unb2b_sdp_station_full-r8026db491            | 2021-11-15    | R vd Walle           | Lofar2 SDP station full design for UniBoard2b.

boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd

@@ -90,7 +90,7 @@ PACKAGE unb2b_board_pkg IS
   CONSTANT c_unb2b_board_tr_jesd204b          : t_c_unb2b_board_tr := (1, 12,  0); -- per node: 1 buses with 12 channels
   CONSTANT c_unb2b_board_nof_tr_jesd204b      : NATURAL := 6;  --Only 6 channels used in unb2b lab tests
   CONSTANT c_unb2b_board_start_tr_jesd204b    : NATURAL := 42; --First transceiver used in unb2b lab tests
-  CONSTANT c_unb2b_board_nof_sync_jesd204b    : NATURAL := 2;  --Only 6 channels used in unb2b lab tests
+  CONSTANT c_unb2b_board_nof_sync_jesd204b    : NATURAL := 4;   -- 4 channels used in unb2b lab tests, 1 for each RCU.
   CONSTANT c_unb2b_board_tr_qsfp_nof_leds     : NATURAL := c_unb2b_board_tr_qsfp.nof_bus * 2; -- 2 leds per qsfp
 
 

libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd

@@ -46,7 +46,7 @@ ENTITY tech_jesd204b_arria10_e1sg IS
     -- JESD204B external signals
     jesd204b_refclk       : IN STD_LOGIC := '0';                             -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
     jesd204b_sysref       : IN STD_LOGIC := '0';                             -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk 
-    jesd204b_sync_n_arr   : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);  -- output to control ADC initialization/syncronization phase
+    jesd204b_sync_n_arr   : OUT STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0);  -- output to control ADC initialization/syncronization phase
     
     jesd204b_disable_arr  : IN STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);