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Commit eeaceac6 authored by Reinier van der Walle's avatar Reinier van der Walle
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added temp alarm to fpga_sense

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1 merge request!177Resolve L2SDP-532
Pipeline #22244 passed
Stage: simulation
Stage: synthesis
Stage: hardware
Pipeline: sdptr

#22245

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    boards/uniboard2b/libraries/unb2b_board/hdllib.cfg
    + 0
    − 1
    View file @ eeaceac6
    ......@@ -26,7 +26,6 @@ synth_files =
    src/vhdl/unb2b_board_hmc_ctrl.vhd
    src/vhdl/unb2b_board_sens.vhd
    src/vhdl/unb2b_board_sens_reg.vhd
    src/vhdl/unb2b_fpga_sens_reg.vhd
    src/vhdl/mms_unb2b_board_sens.vhd
    src/vhdl/mms_unb2b_fpga_sens.vhd
    src/vhdl/unb2b_board_wdi_reg.vhd
    ......
    boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
    + 19
    − 59
    View file @ eeaceac6
    ......@@ -22,7 +22,7 @@
    -- Purpose : MMS for unb2b_fpga_sens
    -- Description: See unb2b_fpga_sens.vhd
    LIBRARY IEEE, technology_lib, common_lib;
    LIBRARY IEEE, technology_lib, common_lib, fpga_sense_lib;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE IEEE.NUMERIC_STD.ALL;
    USE common_lib.common_pkg.ALL;
    ......@@ -43,10 +43,10 @@ ENTITY mms_unb2b_fpga_sens IS
    mm_start : IN STD_LOGIC;
    -- Memory-mapped clock domain
    reg_temp_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
    reg_temp_miso : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
    reg_voltage_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
    reg_voltage_miso : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
    reg_temp_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
    reg_temp_miso : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
    reg_voltage_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
    reg_voltage_miso : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
    -- Temperature alarm output
    temp_alarm : OUT STD_LOGIC
    ......@@ -56,67 +56,27 @@ END mms_unb2b_fpga_sens;
    ARCHITECTURE str OF mms_unb2b_fpga_sens IS
    CONSTANT c_sens_nof_result : NATURAL := 1; --
    CONSTANT c_temp_high_w : NATURAL := 7; -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
    SIGNAL sens_err : STD_LOGIC;
    SIGNAL sens_data : t_slv_8_arr(0 TO c_sens_nof_result-1);
    SIGNAL temp_high : STD_LOGIC_VECTOR(c_temp_high_w-1 DOWNTO 0);
    BEGIN
    u_unb2b_fpga_sens_reg : ENTITY work.unb2b_fpga_sens_reg
    u_fpga_sense: ENTITY fpga_sense_lib.fpga_sense
    GENERIC MAP (
    g_sim => g_sim,
    g_technology => g_technology,
    g_sens_nof_result => c_sens_nof_result,
    g_temp_high => g_temp_high
    g_technology => g_technology,
    g_sim => g_sim,
    g_temp_high => g_temp_high
    )
    PORT MAP (
    -- Clocks and reset
    mm_rst => mm_rst,
    mm_clk => mm_clk,
    start => mm_start,
    -- Memory Mapped Slave in mm_clk domain
    sla_temp_in => reg_temp_mosi,
    sla_temp_out => reg_temp_miso,
    sla_voltage_in => reg_voltage_mosi,
    sla_voltage_out => reg_voltage_miso,
    -- MM registers
    --sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
    --sens_data => sens_data,
    mm_clk => mm_clk,
    mm_rst => mm_rst,
    -- Max temp threshold
    temp_high => temp_high
    );
    -- u_unb2b_board_sens : ENTITY work.unb2b_board_sens
    -- GENERIC MAP (
    -- g_sim => g_sim,
    -- g_clk_freq => g_clk_freq,
    -- g_temp_high => g_temp_high,
    -- g_sens_nof_result => c_sens_nof_result
    -- )
    -- PORT MAP (
    -- clk => mm_clk,
    -- rst => mm_rst,
    -- start => mm_start,
    -- -- i2c bus
    -- scl => scl,
    -- sda => sda,
    -- -- read results
    -- sens_evt => OPEN,
    -- sens_err => sens_err,
    -- sens_data => sens_data
    -- );
    start_sense => mm_start,
    temp_alarm => temp_alarm,
    -- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
    -- would produce -1 degrees so does not trigger a temperature alarm.
    -- temp_high is 7 bits, preceded by a '0' to allow only positive temps to be set.
    temp_alarm <= '0';--<= '1' WHEN (SIGNED(sens_data(0)) > SIGNED('0' & temp_high)) ELSE '0';
    reg_temp_mosi => reg_temp_mosi,
    reg_temp_miso => reg_temp_miso,
    reg_voltage_store_mosi => reg_voltage_mosi,
    reg_voltage_store_miso => reg_voltage_miso
    );
    END str;
    boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_fpga_sens_reg.vhd deleted 100644 → 0
    + 0
    − 89
    View file @ 672d924e
    -------------------------------------------------------------------------------
    --
    -- Copyright (C) 2012-2014
    -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
    -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
    --
    -- This program is free software: you can redistribute it and/or modify
    -- it under the terms of the GNU General Public License as published by
    -- the Free Software Foundation, either version 3 of the License, or
    -- (at your option) any later version.
    --
    -- This program is distributed in the hope that it will be useful,
    -- but WITHOUT ANY WARRANTY; without even the implied warranty of
    -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
    -- GNU General Public License for more details.
    --
    -- You should have received a copy of the GNU General Public License
    -- along with this program. If not, see <http://www.gnu.org/licenses/>.
    --
    -------------------------------------------------------------------------------
    -- Purpose: Provide MM slave register for unb2b_fpga_sens
    --
    LIBRARY IEEE, common_lib, technology_lib, fpga_sense_lib;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE IEEE.NUMERIC_STD.ALL;
    USE common_lib.common_pkg.ALL;
    USE common_lib.common_mem_pkg.ALL;
    USE technology_lib.technology_pkg.ALL;
    ENTITY unb2b_fpga_sens_reg IS
    GENERIC (
    g_sim : BOOLEAN;
    g_technology : NATURAL := c_tech_arria10;
    g_sens_nof_result : NATURAL := 1;
    g_temp_high : NATURAL := 85
    );
    PORT (
    -- Clocks and reset
    mm_rst : IN STD_LOGIC; -- reset synchronous with mm_clk
    mm_clk : IN STD_LOGIC; -- memory-mapped bus clock
    start : IN STD_LOGIC;
    -- Memory Mapped Slave in mm_clk domain
    sla_temp_in : IN t_mem_mosi; -- actual ranges defined by c_mm_reg
    sla_temp_out : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
    sla_voltage_in : IN t_mem_mosi; -- actual ranges defined by c_mm_reg
    sla_voltage_out : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
    -- MM registers
    --sens_err : IN STD_LOGIC := '0';
    --sens_data : IN t_slv_8_arr(0 TO g_sens_nof_result-1); -- FIXME should be OUT
    -- Max temp output
    temp_high : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
    );
    END unb2b_fpga_sens_reg;
    ARCHITECTURE str OF unb2b_fpga_sens_reg IS
    --SIGNAL i_temp_high : STD_LOGIC_VECTOR(6 DOWNTO 0);
    BEGIN
    temp_high <= (others => '0'); --i_temp_high;
    u_fpga_sense: ENTITY fpga_sense_lib.fpga_sense
    GENERIC MAP (
    g_technology => g_technology,
    g_sim => g_sim
    )
    PORT MAP (
    mm_clk => mm_clk,
    mm_rst => mm_rst,
    start_sense => start,
    reg_temp_mosi => sla_temp_in,
    reg_temp_miso => sla_temp_out,
    reg_voltage_store_mosi => sla_voltage_in,
    reg_voltage_store_miso => sla_voltage_out
    );
    END str;
    boards/uniboard2c/libraries/unb2c_board/hdllib.cfg
    + 0
    − 1
    View file @ eeaceac6
    ......@@ -20,7 +20,6 @@ synth_files =
    src/vhdl/unb2c_board_clk125_pll.vhd
    src/vhdl/unb2c_board_wdi_extend.vhd
    src/vhdl/unb2c_board_node_ctrl.vhd
    src/vhdl/unb2c_fpga_sens_reg.vhd
    src/vhdl/mms_unb2c_fpga_sens.vhd
    src/vhdl/unb2c_board_wdi_reg.vhd
    src/vhdl/unb2c_board_qsfp_leds.vhd
    ......
    boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
    + 20
    − 60
    View file @ eeaceac6
    ......@@ -43,10 +43,10 @@ ENTITY mms_unb2c_fpga_sens IS
    mm_start : IN STD_LOGIC;
    -- Memory-mapped clock domain
    reg_temp_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
    reg_temp_miso : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
    reg_voltage_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
    reg_voltage_miso : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
    reg_temp_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
    reg_temp_miso : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
    reg_voltage_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
    reg_voltage_miso : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
    -- Temperature alarm output
    temp_alarm : OUT STD_LOGIC
    ......@@ -56,67 +56,27 @@ END mms_unb2c_fpga_sens;
    ARCHITECTURE str OF mms_unb2c_fpga_sens IS
    CONSTANT c_sens_nof_result : NATURAL := 1; --
    CONSTANT c_temp_high_w : NATURAL := 7; -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
    SIGNAL sens_err : STD_LOGIC;
    SIGNAL sens_data : t_slv_8_arr(0 TO c_sens_nof_result-1);
    SIGNAL temp_high : STD_LOGIC_VECTOR(c_temp_high_w-1 DOWNTO 0);
    BEGIN
    u_unb2c_fpga_sens_reg : ENTITY work.unb2c_fpga_sens_reg
    u_fpga_sense: ENTITY fpga_sense_lib.fpga_sense
    GENERIC MAP (
    g_sim => g_sim,
    g_technology => g_technology,
    g_sens_nof_result => c_sens_nof_result,
    g_temp_high => g_temp_high
    g_technology => g_technology,
    g_sim => g_sim,
    g_temp_high => g_temp_high
    )
    PORT MAP (
    -- Clocks and reset
    mm_rst => mm_rst,
    mm_clk => mm_clk,
    start => mm_start,
    -- Memory Mapped Slave in mm_clk domain
    sla_temp_in => reg_temp_mosi,
    sla_temp_out => reg_temp_miso,
    sla_voltage_in => reg_voltage_mosi,
    sla_voltage_out => reg_voltage_miso,
    -- MM registers
    --sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
    --sens_data => sens_data,
    mm_clk => mm_clk,
    mm_rst => mm_rst,
    -- Max temp threshold
    temp_high => temp_high
    );
    -- u_unb2c_board_sens : ENTITY work.unb2c_board_sens
    -- GENERIC MAP (
    -- g_sim => g_sim,
    -- g_clk_freq => g_clk_freq,
    -- g_temp_high => g_temp_high,
    -- g_sens_nof_result => c_sens_nof_result
    -- )
    -- PORT MAP (
    -- clk => mm_clk,
    -- rst => mm_rst,
    -- start => mm_start,
    -- -- i2c bus
    -- scl => scl,
    -- sda => sda,
    -- -- read results
    -- sens_evt => OPEN,
    -- sens_err => sens_err,
    -- sens_data => sens_data
    -- );
    start_sense => mm_start,
    temp_alarm => temp_alarm,
    -- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
    -- would produce -1 degrees so does not trigger a temperature alarm.
    -- temp_high is 7 bits, preceded by a '0' to allow only positive temps to be set.
    temp_alarm <= '0';--<= '1' WHEN (SIGNED(sens_data(0)) > SIGNED('0' & temp_high)) ELSE '0';
    reg_temp_mosi => reg_temp_mosi,
    reg_temp_miso => reg_temp_miso,
    reg_voltage_store_mosi => reg_voltage_mosi,
    reg_voltage_store_miso => reg_voltage_miso
    );
    END str;
    boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_fpga_sens_reg.vhd deleted 100644 → 0
    + 0
    − 89
    View file @ 672d924e
    -------------------------------------------------------------------------------
    --
    -- Copyright (C) 2012-2014
    -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
    -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
    --
    -- This program is free software: you can redistribute it and/or modify
    -- it under the terms of the GNU General Public License as published by
    -- the Free Software Foundation, either version 3 of the License, or
    -- (at your option) any later version.
    --
    -- This program is distributed in the hope that it will be useful,
    -- but WITHOUT ANY WARRANTY; without even the implied warranty of
    -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
    -- GNU General Public License for more details.
    --
    -- You should have received a copy of the GNU General Public License
    -- along with this program. If not, see <http://www.gnu.org/licenses/>.
    --
    -------------------------------------------------------------------------------
    -- Purpose: Provide MM slave register for unb2c_fpga_sens
    --
    LIBRARY IEEE, common_lib, technology_lib, fpga_sense_lib;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE IEEE.NUMERIC_STD.ALL;
    USE common_lib.common_pkg.ALL;
    USE common_lib.common_mem_pkg.ALL;
    USE technology_lib.technology_pkg.ALL;
    ENTITY unb2c_fpga_sens_reg IS
    GENERIC (
    g_sim : BOOLEAN;
    g_technology : NATURAL := c_tech_arria10;
    g_sens_nof_result : NATURAL := 1;
    g_temp_high : NATURAL := 85
    );
    PORT (
    -- Clocks and reset
    mm_rst : IN STD_LOGIC; -- reset synchronous with mm_clk
    mm_clk : IN STD_LOGIC; -- memory-mapped bus clock
    start : IN STD_LOGIC;
    -- Memory Mapped Slave in mm_clk domain
    sla_temp_in : IN t_mem_mosi; -- actual ranges defined by c_mm_reg
    sla_temp_out : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
    sla_voltage_in : IN t_mem_mosi; -- actual ranges defined by c_mm_reg
    sla_voltage_out : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
    -- MM registers
    --sens_err : IN STD_LOGIC := '0';
    --sens_data : IN t_slv_8_arr(0 TO g_sens_nof_result-1); -- FIXME should be OUT
    -- Max temp output
    temp_high : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
    );
    END unb2c_fpga_sens_reg;
    ARCHITECTURE str OF unb2c_fpga_sens_reg IS
    --SIGNAL i_temp_high : STD_LOGIC_VECTOR(6 DOWNTO 0);
    BEGIN
    temp_high <= (others => '0'); --i_temp_high;
    u_fpga_sense: ENTITY fpga_sense_lib.fpga_sense
    GENERIC MAP (
    g_technology => g_technology,
    g_sim => g_sim
    )
    PORT MAP (
    mm_clk => mm_clk,
    mm_rst => mm_rst,
    start_sense => start,
    reg_temp_mosi => sla_temp_in,
    reg_temp_miso => sla_temp_out,
    reg_voltage_store_mosi => sla_voltage_in,
    reg_voltage_store_miso => sla_voltage_out
    );
    END str;
    libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd
    + 11
    − 3
    View file @ eeaceac6
    ......@@ -37,7 +37,8 @@ USE technology_lib.technology_pkg.ALL;
    ENTITY fpga_sense IS
    GENERIC (
    g_technology : NATURAL := c_tech_select_default;
    g_sim : BOOLEAN
    g_sim : BOOLEAN;
    g_temp_high : NATURAL := 85
    );
    PORT (
    -- MM interface
    ......@@ -45,6 +46,7 @@ ENTITY fpga_sense IS
    mm_clk : IN STD_LOGIC;
    start_sense : IN STD_LOGIC;
    temp_alarm : OUT STD_LOGIC;
    reg_temp_mosi : IN t_mem_mosi := c_mem_mosi_rst;
    reg_temp_miso : OUT t_mem_miso;
    ......@@ -63,6 +65,9 @@ ARCHITECTURE str OF fpga_sense IS
    CONSTANT c_mem_reg_temp_nof_data : NATURAL := 1;
    CONSTANT c_mem_reg_temp_data : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_temp_adr_w , c_mem_reg_temp_dat_w , c_mem_reg_temp_nof_data, 'X');
    -- temp = (708 * adc)/1024 - 273 => adc = (temp + 273)*1024/708
    CONSTANT c_temp_high_raw : STD_LOGIC_VECTOR(9 downto 0) := TO_UVEC(((g_temp_high + 273) * 1024) / 708, 10);
    -- constants for the voltage sensor
    CONSTANT c_mem_reg_voltage_adr_w : NATURAL := 1;
    CONSTANT c_mem_reg_voltage_dat_w : NATURAL := 32;
    ......@@ -84,7 +89,7 @@ ARCHITECTURE str OF fpga_sense IS
    BEGIN
    -- temperature sensor
    temp_alarm <= '1' WHEN (SIGNED(temp_data) > SIGNED(c_temp_high_raw)) ELSE '0';
    gen_tech_fpga_temp_sens: IF g_sim=FALSE GENERATE
    u_tech_fpga_temp_sens : ENTITY tech_fpga_temp_sens_lib.tech_fpga_temp_sens
    GENERIC MAP (
    ......@@ -173,13 +178,16 @@ BEGIN
    BEGIN
    IF mm_rst = '1' THEN
    controller_csr_write <= '0';
    start_sense_mm <= '0';
    start_sense_mm_d1 <= '0';
    start_sense_mm_d2 <= '0';
    ELSIF rising_edge(mm_clk) THEN
    start_sense_mm <= start_sense;
    start_sense_mm_d1 <= start_sense_mm;
    start_sense_mm_d2 <= start_sense_mm_d1;
    if start_sense_mm_d1 = '1' and start_sense_mm_d2 = '0' then
    controller_csr_write <= '1';
    else
    else
    controller_csr_write <= '0';
    end if;
    END IF;
    ......
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