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Commit ee3f6786 authored by Pieter Donker's avatar Pieter Donker
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CWG-44, add linting for vhdl, test3

parent 8235494a
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1 merge request!316Resolve CWG-44
Pipeline #46073 passed
...@@ -37,8 +37,6 @@ lint-vhdl-lib-base: ...@@ -37,8 +37,6 @@ lint-vhdl-lib-base:
stage: linting stage: linting
allow_failure: true allow_failure: true
before_script: before_script:
#- DEBIAN_FRONTEND=noninteractive apt-get update
#- DEBIAN_FRONTEND=noninteractive apt-get install -y python3 python3-pip python3-ipython
- pip3 install vsg --use-pep517 - pip3 install vsg --use-pep517
script: script:
- cd libraries/base - cd libraries/base
...@@ -77,6 +75,49 @@ lint-vhdl-lib-technology: ...@@ -77,6 +75,49 @@ lint-vhdl-lib-technology:
- cd libraries/technology - cd libraries/technology
- find . -name "*.vhd" -exec vsg --configuration ../../vsg_config.yaml -f {} \; - find . -name "*.vhd" -exec vsg --configuration ../../vsg_config.yaml -f {} \;
lint-vhdl-boards-uniboard2b:
tags:
- hdl
stage: linting
allow_failure: true
before_script:
- pip3 install vsg --use-pep517
script:
- cd boards/uniboard2b
- find . -name "*.vhd" -exec vsg --configuration ../../vsg_config.yaml -f {} \;
lint-vhdl-boards-uniboard2c:
tags:
- hdl
stage: linting
allow_failure: true
before_script:
- pip3 install vsg --use-pep517
script:
- cd boards/uniboard2c
- find . -name "*.vhd" -exec vsg --configuration ../../vsg_config.yaml -f {} \;
lint-vhdl-applications-disturb2:
tags:
- hdl
stage: linting
allow_failure: true
before_script:
- pip3 install vsg --use-pep517
script:
- cd applications/disturb2
- find . -name "*.vhd" -exec vsg --configuration ../../vsg_config.yaml -f {} \;
lint-vhdl-applications-lofar2:
tags:
- hdl
stage: linting
allow_failure: true
before_script:
- pip3 install vsg --use-pep517
script:
- cd applications/lofar2
- find . -name "*.vhd" -exec vsg --configuration ../../vsg_config.yaml -f {} \;
############################################################################### ###############################################################################
# HDL simulation stage # HDL simulation stage
......
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