-Added MM bus for dp_offload_tx instance;

-Set working default header fields;
-Added gen_ip_header_checksum.

applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer_udp_offload.vhd

@@ -70,7 +70,7 @@ ARCHITECTURE wrap OF apertif_unb1_fn_beamformer_udp_offload IS
   CONSTANT c_nof_offload_streams       : NATURAL := 1; 
 
   -- Override ('1') only the Ethernet fields so we can use MM defaults there.
-  CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_apertif_udp_offload_nof_hdr_fields-1 DOWNTO 0) := "101"&"111111111101"&"0011"&"100";
+  CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_apertif_udp_offload_nof_hdr_fields-1 DOWNTO 0) := "101"&"111111111111"&"1111"&"100";
 
   CONSTANT c_bf_out_compl_dat_w        : NATURAL := 8;
   CONSTANT c_data_w                    : NATURAL := 64; -- 4 BF units * 8b complex

applications/apertif/designs/apertif_unb1_fn_bf_emu/quartus/sopc_apertif_unb1_fn_bf_emu.sopc

@@ -92,7 +92,7 @@
          type = "String";
       }
    }
-   element reg_wdi.mem
+   element rom_system_info.mem
    {
       datum _lockedAddress
       {
@@ -101,89 +101,84 @@
       }
       datum baseAddress
       {
-         value = "12288";
+         value = "4096";
          type = "long";
       }
    }
-   element reg_diag_bg.mem
+   element pio_pps.mem
    {
       datum baseAddress
       {
-         value = "256";
+         value = "440";
          type = "long";
       }
    }
-   element reg_tr_xaui.mem
+   element pio_system_info.mem
+   {
+      datum _lockedAddress
       {
+         value = "1";
+         type = "boolean";
+      }
       datum baseAddress
       {
-         value = "32768";
+         value = "0";
          type = "long";
       }
    }
-   element pio_pps.mem
+   element reg_tr_10GbE.mem
    {
       datum baseAddress
       {
-         value = "440";
+         value = "262144";
          type = "long";
       }
    }
-   element reg_mdio_2.mem
+   element ram_diag_bg.mem
    {
       datum baseAddress
       {
-         value = "352";
+         value = "32768";
          type = "long";
       }
    }
-   element pio_system_info.mem
-   {
-      datum _lockedAddress
+   element reg_tr_xaui.mem
    {
-         value = "1";
-         type = "boolean";
-      }
       datum baseAddress
       {
-         value = "0";
+         value = "32768";
          type = "long";
       }
    }
-   element reg_mdio_1.mem
+   element reg_diag_bg.mem
    {
       datum baseAddress
       {
-         value = "320";
+         value = "256";
          type = "long";
       }
    }
-   element rom_system_info.mem
-   {
-      datum _lockedAddress
+   element reg_dp_offload_tx_hdr_dat.mem
    {
-         value = "1";
-         type = "boolean";
-      }
       datum baseAddress
       {
-         value = "4096";
+         value = "512";
          type = "long";
       }
    }
-   element ram_diag_bg.mem
+   element reg_mdio_0.mem
    {
       datum baseAddress
       {
-         value = "32768";
+         value = "288";
          type = "long";
       }
    }
-   element reg_tr_10GbE.mem
+   element reg_mdio_1.mem
    {
       datum baseAddress
       {
-         value = "262144";
+         value = "320";
          type = "long";
       }
    }
@@ -195,11 +190,24 @@
          type = "long";
       }
    }
-   element reg_mdio_0.mem
+   element reg_mdio_2.mem
    {
       datum baseAddress
       {
-         value = "288";
+         value = "352";
+         type = "long";
+      }
+   }
+   element reg_wdi.mem
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "12288";
          type = "long";
       }
    }
@@ -311,6 +319,14 @@
          type = "int";
       }
    }
+   element reg_dp_offload_tx_hdr_dat
+   {
+      datum _sortIndex
+      {
+         value = "21";
+         type = "int";
+      }
+   }
    element reg_mdio_0
    {
       datum _sortIndex
@@ -388,32 +404,32 @@
          type = "long";
       }
    }
-   element onchip_memory2_0.s1
-   {
-      datum _lockedAddress
+   element timer_0.s1
    {
-         value = "1";
-         type = "boolean";
-      }
       datum baseAddress
       {
-         value = "131072";
+         value = "192";
          type = "long";
       }
    }
-   element timer_0.s1
+   element pio_debug_wave.s1
    {
       datum baseAddress
       {
-         value = "192";
+         value = "400";
          type = "long";
       }
    }
-   element pio_debug_wave.s1
+   element onchip_memory2_0.s1
    {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
       datum baseAddress
       {
-         value = "400";
+         value = "131072";
          type = "long";
       }
    }
@@ -445,10 +461,10 @@
  <parameter name="globalResetBus" value="true" />
  <parameter name="hdlLanguage" value="VHDL" />
  <parameter name="maxAdditionalLatency" value="0" />
- <parameter name="projectName" value="" />
+ <parameter name="projectName">apertif_unb1_fn_bf_emu.qpf</parameter>
  <parameter name="sopcBorderPoints" value="true" />
- <parameter name="systemHash" value="-29495268338" />
- <parameter name="timeStamp" value="1467364000854" />
+ <parameter name="systemHash" value="-32699227954" />
+ <parameter name="timeStamp" value="1477552867077" />
  <parameter name="useTestBenchNamingPattern" value="false" />
  <module kind="clock_source" version="11.1" enabled="1" name="clk_0">
   <parameter name="clockFrequency" value="25000000" />
@@ -549,7 +565,7 @@
   <parameter name="dcache_numTCDM" value="_0" />
   <parameter name="dcache_lineSize" value="_32" />
   <parameter name="dcache_bursts" value="false" />
-  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='reg_diag_bg.mem' start='0x100' end='0x120' /><slave name='reg_mdio_0.mem' start='0x120' end='0x140' /><slave name='reg_mdio_1.mem' start='0x140' end='0x160' /><slave name='reg_mdio_2.mem' start='0x160' end='0x180' /><slave name='altpll_0.pll_slave' start='0x180' end='0x190' /><slave name='pio_debug_wave.s1' start='0x190' end='0x1A0' /><slave name='pio_wdi.s1' start='0x1A0' end='0x1B0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1B0' end='0x1B8' /><slave name='pio_pps.mem' start='0x1B8' end='0x1C0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='reg_tr_xaui.mem' start='0x8000' end='0x10000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /></address-map>]]></parameter>
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='reg_diag_bg.mem' start='0x100' end='0x120' /><slave name='reg_mdio_0.mem' start='0x120' end='0x140' /><slave name='reg_mdio_1.mem' start='0x140' end='0x160' /><slave name='reg_mdio_2.mem' start='0x160' end='0x180' /><slave name='altpll_0.pll_slave' start='0x180' end='0x190' /><slave name='pio_debug_wave.s1' start='0x190' end='0x1A0' /><slave name='pio_wdi.s1' start='0x1A0' end='0x1B0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1B0' end='0x1B8' /><slave name='pio_pps.mem' start='0x1B8' end='0x1C0' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x200' end='0x280' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='reg_tr_xaui.mem' start='0x8000' end='0x10000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /></address-map>]]></parameter>
   <parameter name="dataAddrWidth" value="19" />
   <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
   <parameter name="cpuReset" value="false" />
@@ -883,6 +899,15 @@ q]]></parameter>
   <parameter name="g_dat_w" value="32" />
   <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
  </module>
+ <module
+   kind="avs_common_mm"
+   version="1.0"
+   enabled="1"
+   name="reg_dp_offload_tx_hdr_dat">
+  <parameter name="g_adr_w" value="5" />
+  <parameter name="g_dat_w" value="32" />
+  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
  <connection
    kind="avalon"
    version="11.1"
@@ -1164,4 +1189,17 @@ q]]></parameter>
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x01b8" />
  </connection>
+ <connection
+   kind="clock"
+   version="11.1"
+   start="altpll_0.c0"
+   end="reg_dp_offload_tx_hdr_dat.system" />
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="reg_dp_offload_tx_hdr_dat.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0200" />
+ </connection>
 </system>

applications/apertif/designs/apertif_unb1_fn_bf_emu/src/python/gen_ip_header_checksum.py

+###############################################################################
+#
+# Copyright (C) 2013
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+from eth import *
+
+################################################################################
+# Constants
+###############################################################################
+
+# Header lengths in bytes
+IP_HEADER_LENGTH  = 20
+UDP_HEADER_LENGTH =  8
+DP_HEADER_LENGTH = 14
+
+# NOF_PAYLOAD_BYTES derived from nof signal paths and dp_offload_tx settings
+
+NOF_BEAMLETS_PER_PACKET = 176  
+NOF_PAYLOAD_BYTES = NOF_BEAMLETS_PER_PACKET * 64 / c_byte_w # 1408B
+
+###############################################################################
+# The IP header field values. All fixed except ip_src_addr 
+# (and concequently the ip_header_checksum).
+###############################################################################
+ip_version         = 4 
+ip_header_length   = 5 # 5 32b words
+ip_services        = 0 
+ip_total_length    = IP_HEADER_LENGTH+UDP_HEADER_LENGTH+DP_HEADER_LENGTH+NOF_PAYLOAD_BYTES 
+print ip_total_length
+ip_identification  = 0 
+ip_flags           = 2 
+ip_fragment_offset = 0 
+ip_time_to_live    = 127 
+ip_protocol        = 17 
+ip_header_checksum = 0 # to be calculated
+ip_src_addr        = 0xc0a80009 # 192.168.0.9
+ip_dst_addr        = 0xc0a80001 # 192.168.0.1
+
+###############################################################################
+# Calculate and print the IP header checksum
+###############################################################################
+hdr_bits = CommonBits(ip_version         ,4)  & \
+           CommonBits(ip_header_length   ,4)  & \
+           CommonBits(ip_services        ,8)  & \
+           CommonBits(ip_total_length    ,16) & \
+           CommonBits(ip_identification  ,16) & \
+           CommonBits(ip_flags           ,3)  & \
+           CommonBits(ip_fragment_offset ,13) & \
+           CommonBits(ip_time_to_live    ,8)  & \
+           CommonBits(ip_protocol        ,8)  & \
+           CommonBits(ip_header_checksum ,16) & \
+           CommonBits(ip_src_addr        ,32) & \
+           CommonBits(ip_dst_addr        ,32)
+
+hdr_bytes = CommonBytes(hdr_bits.data, 20)
+
+print ip_hdr_checksum(hdr_bytes)

applications/apertif/designs/apertif_unb1_fn_bf_emu/src/vhdl/apertif_unb1_fn_bf_emu.vhd

@@ -204,6 +204,8 @@ ARCHITECTURE str OF apertif_unb1_fn_bf_emu IS
   SIGNAL reg_tr_xaui_miso           : t_mem_miso := c_mem_miso_rst;
   SIGNAL reg_mdio_mosi_arr          : t_mem_mosi_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
   SIGNAL reg_mdio_miso_arr          : t_mem_miso_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);     
+  SIGNAL reg_dp_offload_tx_hdr_dat_mosi_arr : t_mem_mosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
+  SIGNAL reg_dp_offload_tx_hdr_dat_miso_arr : t_mem_miso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
 
 BEGIN
 
@@ -270,8 +272,8 @@ BEGIN
   
       reg_dp_offload_tx_mosi         => c_mem_mosi_rst,
       reg_dp_offload_tx_miso         => OPEN,
-      reg_dp_offload_tx_hdr_dat_mosi => c_mem_mosi_rst,
-      reg_dp_offload_tx_hdr_dat_miso => OPEN
+      reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi_arr(i),
+      reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso_arr(i)
     );
   END GENERATE;
 
@@ -432,6 +434,9 @@ BEGIN
     reg_tr_xaui_mosi           => reg_tr_xaui_mosi,               
     reg_tr_xaui_miso           => reg_tr_xaui_miso,    
      
+    reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi_arr(0),
+    reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso_arr(0), 
+ 
     -- eth1g     
     eth1g_tse_clk              => eth1g_tse_clk,                  
     eth1g_mm_rst               => eth1g_mm_rst,                   

applications/apertif/designs/apertif_unb1_fn_bf_emu/src/vhdl/mmm_apertif_unb1_fn_bf_emu.vhd

@@ -96,6 +96,9 @@ ENTITY mmm_apertif_unb1_fn_bf_emu IS
     reg_tr_xaui_mosi               : OUT t_mem_mosi;
     reg_tr_xaui_miso               : IN  t_mem_miso := c_mem_miso_rst;
 
+    reg_dp_offload_tx_hdr_dat_mosi : OUT t_mem_mosi;
+    reg_dp_offload_tx_hdr_dat_miso : IN  t_mem_miso := c_mem_miso_rst;
+
     -- eth1g
     eth1g_tse_clk                  : OUT STD_LOGIC;
     eth1g_mm_rst                   : OUT STD_LOGIC;
@@ -124,6 +127,7 @@ ARCHITECTURE str OF mmm_apertif_unb1_fn_bf_emu IS
   CONSTANT c_xaui_mosi_addr_w                    : NATURAL := ceil_log2(3*(2**9)); --2^9 = range of 512 addresses
   CONSTANT c_max_nof_xaui_inst                   : NATURAL := 4;
   CONSTANT c_reg_tr_xaui_addr_w                  : NATURAL := ceil_log2(c_max_nof_xaui_inst* pow2(c_xaui_mosi_addr_w)); -- 4* 512 = 2048 addresses -> 11 address bits.
+  CONSTANT c_reg_dp_offload_tx_hdr_dat_addr_w    : NATURAL := 5;
 
   -- Simulation
   CONSTANT c_mm_clk_period  : TIME := 800 ns;
@@ -403,7 +407,17 @@ BEGIN
       coe_readdata_export_to_the_reg_tr_xaui                  => reg_tr_xaui_miso.rddata(c_word_w-1 DOWNTO 0),
       coe_waitrequest_export_to_the_reg_tr_xaui               => reg_tr_xaui_miso.waitrequest,
       coe_write_export_from_the_reg_tr_xaui                   => reg_tr_xaui_mosi.wr,
-      coe_writedata_export_from_the_reg_tr_xaui               => reg_tr_xaui_mosi.wrdata(c_word_w-1 DOWNTO 0)
+      coe_writedata_export_from_the_reg_tr_xaui               => reg_tr_xaui_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      -- the_reg_dp_offload_tx_hdr_dat 
+      coe_clk_export_from_the_reg_dp_offload_tx_hdr_dat       => OPEN,
+      coe_reset_export_from_the_reg_dp_offload_tx_hdr_dat     => OPEN,
+      coe_address_export_from_the_reg_dp_offload_tx_hdr_dat   => reg_dp_offload_tx_hdr_dat_mosi.address(c_reg_dp_offload_tx_hdr_dat_addr_w-1 DOWNTO 0),
+      coe_read_export_from_the_reg_dp_offload_tx_hdr_dat      => reg_dp_offload_tx_hdr_dat_mosi.rd,
+      coe_readdata_export_to_the_reg_dp_offload_tx_hdr_dat    => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+--      coe_waitrequest_export_to_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_miso.waitrequest,
+      coe_write_export_from_the_reg_dp_offload_tx_hdr_dat     => reg_dp_offload_tx_hdr_dat_mosi.wr,
+      coe_writedata_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0)
     );
   END GENERATE;