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RTSD
HDL
Commits
ee0edfcb
Commit
ee0edfcb
authored
2 years ago
by
Eric Kooistra
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Describe using jtag prgrammer on DTS-lab.
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94599e2b
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!294
Resolve L2SDP-837
Pipeline
#40278
passed
2 years ago
Stage: simulation
Stage: synthesis
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doc/erko_howto_tools.txt
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ee0edfcb
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@@ -25,7 +25,7 @@
* Zenodo DOI
* Install OpenSCAD
* Drawio
* DTS-lab unb2c
...
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@@ -137,6 +137,7 @@ gen_rom_mmap.py --avalon -d unb2c_test -r unb2c_test_1GbE_I
run_reg unb2c unb2c_test_1GbE_I
run_qcomp unb2c unb2c_test_1GbE_I --clk=CLK
run_rbf unb2c unb2c_test_1GbE_I
==> All in one: build_image unb2c unb2c_test --rev=unb2c_test_1GbE_I --seed=1,2
quartus_config unb2c
run_qsys_pro unb2c unb2c_test_1GbE_II
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@@ -1169,3 +1170,23 @@ Gelukt !
Oude drawio uninstall mbv Administration/Software Manager
Nieuw heet nu diagrams.net 18.1.3 installed mbv Administration/Software Manager
Alt-F7 to move window on screen
*******************************************************************************
* DTS-lab unb2c
*******************************************************************************
> mystep
> Program FPGA using USB programmer:
> run_quartus unb2c &
- Open programmer via button icon --> Hardware setup --> Add hardware
Server name 10.87.6.204 (lab laptop) password: uniboard
JTAG settings (OK)
Hardware settings dubbel click
Auto detect
Select FPGA --> change file (sof) --> select Program/Reconfigure --> Start
> Via dop421 upe_gear:
. ./init_upe.sh
mkdir reginfo
util_unb2.py --unb2 0 --pn2 0:3 --seq REGMAPt
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