Merge branch 'master' of git.astron.nl:desp/hdl

applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/opencl_bsp_ip.qsf

+# (C) 1992-2018 Intel Corporation.                            
+# Intel, the Intel logo, Intel, MegaCore, NIOS II, Quartus and TalkBack words    
+# and logos are trademarks of Intel Corporation or its subsidiaries in the U.S.  
+# and/or other countries. Other marks and brands may be claimed as the property  
+# of others. See Trademarks on intel.com for full list of Intel trademarks or    
+# the Trademarks & Brands Names Database (if Intel) or See www.Intel.com/legal (if Altera) 
+# Your use of Intel Corporation's design tools, logic functions and other        
+# software and tools, and its AMPP partner logic functions, and any output       
+# files any of the foregoing (including device programming or simulation         
+# files), and any associated documentation or information are expressly subject  
+# to the terms and conditions of the Altera Program License Subscription         
+# Agreement, Intel MegaCore Function License Agreement, or other applicable      
+# license agreement, including, without limitation, that your use is for the     
+# sole purpose of programming logic devices manufactured by Intel and sold by    
+# Intel or its authorized distributors.  Please refer to the applicable          
+# agreement for further details.                                                 
+
+
+# device.tcl contains settings unique to each device type/board variant (most importantly, the device string for the particular device type)
+source device.tcl
+
+#============================================================
+# Files and basic settings
+#============================================================
+set_global_assignment -name TOP_LEVEL_ENTITY top
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+#set_global_assignment -name VHDL_FILE top_components_pkg.vhd
+#set_global_assignment -name VHDL_FILE top.vhd
+#set_global_assignment -name VERILOG_FILE ip/freeze_wrapper.v
+#set_global_assignment -name VERILOG_FILE ip/pr_region.v
+set_global_assignment -name LAST_QUARTUS_VERSION "19.2.0 Pro Edition"
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name DEVICE 10AX115U2F45E1SG
+set_global_assignment -name FAMILY "Arria 10"
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1932
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 4
+
+set_global_assignment -name SOURCE_TCL_SCRIPT_FILE radiohdl_components.qsf
+
+set_global_assignment -name QSYS_FILE board.qsys
+
+set_global_assignment -name IP_FILE ip/board/board_reg_unb_pmbus.ip
+set_global_assignment -name IP_FILE ip/board/board_kernel_clk_gen.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_epcs.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_mmdp_ctrl.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_mmdp_data.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_dpmm_ctrl.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_dpmm_data.ip
+set_global_assignment -name IP_FILE ip/board/board_cpu_0.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_fpga_voltage_sens.ip
+set_global_assignment -name IP_FILE ip/board/board_onchip_memory2_0.ip
+set_global_assignment -name IP_FILE ip/board/board_clk_0.ip
+set_global_assignment -name IP_FILE ip/board/board_pio_system_info.ip
+set_global_assignment -name IP_FILE ip/board/board_kernel_interface.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_wdi.ip
+set_global_assignment -name IP_FILE ip/board/board_pio_pps.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_unb_sens.ip
+set_global_assignment -name IP_FILE ip/board/board_avs_eth_0.ip
+set_global_assignment -name IP_FILE ip/board/board_timer_0.ip
+set_global_assignment -name IP_FILE ip/board/board_rom_system_info.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_fpga_temp_sens.ip
+set_global_assignment -name IP_FILE ip/board/board_pio_wdi.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_remu.ip
+set_global_assignment -name IP_FILE ip/board/board_jtag_uart_0.ip
+set_global_assignment -name IP_FILE ip/board/board_kernel_clk.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_ta2_unb2b_mm_io.ip
+set_global_assignment -name IP_FILE ip/board/board_ram_scrap.ip
+set_global_assignment -name IP_FILE ip/board/board_kclk_global.ip
+set_global_assignment -name IP_FILE ip/board/board_ram_diag_bg_ring.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_diag_bg_ring.ip

applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/scripts/post_flow_pr.tcl

+# (C) 1992-2018 Intel Corporation.                            
+# Intel, the Intel logo, Intel, MegaCore, NIOS II, Quartus and TalkBack words    
+# and logos are trademarks of Intel Corporation or its subsidiaries in the U.S.  
+# and/or other countries. Other marks and brands may be claimed as the property  
+# of others. See Trademarks on intel.com for full list of Intel trademarks or    
+# the Trademarks & Brands Names Database (if Intel) or See www.Intel.com/legal (if Altera) 
+# Your use of Intel Corporation's design tools, logic functions and other        
+# software and tools, and its AMPP partner logic functions, and any output       
+# files any of the foregoing (including device programming or simulation         
+# files), and any associated documentation or information are expressly subject  
+# to the terms and conditions of the Altera Program License Subscription         
+# Agreement, Intel MegaCore Function License Agreement, or other applicable      
+# license agreement, including, without limitation, that your use is for the     
+# sole purpose of programming logic devices manufactured by Intel and sold by    
+# Intel or its authorized distributors.  Please refer to the applicable          
+# agreement for further details.                                                 
+# ##########################################################################
+# Copyright 2020
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# ##########################################################################
+
+# ##########################################################################
+# Author:
+# . Reinier vd Walle 
+# Purpose:
+# . post-compile script for OpenCL applications
+# Description:
+# . " "
+# ##########################################################################
+post_message "Running post_flow_pr.tcl script"
+
+post_message "Checking for OpenCL SDK installation, environment should have INTELFPGAOCLSDKROOT defined"
+if {[catch {set sdk_root $::env(INTELFPGAOCLSDKROOT)} result]} {
+  post_message -type error "OpenCL SDK installation not found.  Make sure INTELFPGAOCLSDKROOT is correctly set"
+  exit 2
+} else {
+  post_message "INTELFPGAOCLSDKROOT=$::env(INTELFPGAOCLSDKROOT)"
+}
+
+# Load OpenCL BSP utility functions
+source "$sdk_root/ip/board/bsp/opencl_bsp_util.tcl"
+
+set project_name  [::opencl_bsp::get_project_name $quartus(args)]
+set revision_name [::opencl_bsp::get_revision_name $quartus(args) $project_name]
+set fast_compile  [::aocl_fast_compile::is_fast_compile]
+set logic_limit 75.0
+set update_mif 1
+
+
+##############################################################################
+##############################       MAIN        #############################
+##############################################################################
+
+post_message "Project name: $project_name"
+post_message "Revision name: $revision_name"
+
+
+# Run adjust PLL script 
+source "$sdk_root/ip/board/bsp/adjust_plls_a10.tcl"
+
+# Copy flat.sof and flat.rbf to parent directory
+if {[file exists "flat_time_limited.sof"] == 1} {
+   post_message "Warning: flat.sof and flat.rbf are Time Limited!"
+   qexec "quartus_cpf -c --option=scripts/rbf_options_file flat_time_limited.sof ../flat.rbf"
+   file copy -force flat_time_limited.sof ../flat.sof
+}
+
+if {[file exists "flat.sof"] == 1} {
+   qexec "quartus_cpf -c --option=scripts/rbf_options_file flat.sof ../flat.rbf"
+   file copy -force flat.sof ../flat.sof
+}
+
+if {$fast_compile} {
+  ::aocl_fast_compile::check_logic_utilization $logic_limit
+}
+

applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/scripts/rbf_options_file

+Bitstream_compression=on