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RTSD
HDL
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Commit
eb5ffebc
authored
Nov 19, 2021
by
Daniel van der Schuur
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-Renamed and added dummy pipeline stages.
parent
3fff762d
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!174
Added .gitlab-ci.yml
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#21026
passed
Nov 19, 2021
Stage: sim-compile
Stage: sim-simulate
Stage: hw-compile
Stage: hw-check-fmax
Stage: hw-check-programming-files
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00:18:14
Nov 19, 2021
-Renamed and added dummy pipeline stages.
#21026
L2SDP-534
eb5ffebc
branch
Stage: sim-compile
Stage: sim-simulate
Stage: hw-compile
Stage: hw-check-fmax
Stage: hw-check-programming-files
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