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RTSD
HDL
Commits
eaafb244
Commit
eaafb244
authored
Oct 11, 2023
by
Eric Kooistra
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Use g_cross_clock_domain = false to save logic.
parent
2d7d72b6
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1 merge request
!360
Resolve L2SDP-965
Pipeline
#60462
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Oct 11, 2023
Stage: linting
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applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_destinations_reg.vhd
+9
-2
9 additions, 2 deletions
...ofar2/libraries/sdp/src/vhdl/sdp_bdo_destinations_reg.vhd
with
9 additions
and
2 deletions
applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_destinations_reg.vhd
+
9
−
2
View file @
eaafb244
...
@@ -208,7 +208,14 @@ begin
...
@@ -208,7 +208,14 @@ begin
u_mm_fields
:
entity
mm_lib
.
mm_fields
u_mm_fields
:
entity
mm_lib
.
mm_fields
generic
map
(
generic
map
(
g_use_slv_in_val
=>
false
,
-- use FALSE to save logic when always slv_in_val='1'
-- With g_nof_destinations_max = 31 and mac_w = 48, ip_w = 32, udp_w = 16
-- the expected logic FF usage is 31 * (48 + 32 + 16) + 4 * 32 ~= 3104 FF.
-- Use g_cross_clock_domain false to save clock domain crossing logic,
-- which is about 2/3 of the total logic (~ 6200 FF). This is save,
-- because the reg fields are set well before they are used, so any meta
-- stability will have settled long before that.
g_cross_clock_domain
=>
false
,
g_use_slv_in_val
=>
false
,
-- use false to save logic when always slv_in_val='1'
g_field_arr
=>
c_field_arr
g_field_arr
=>
c_field_arr
)
)
port
map
(
port
map
(
...
...
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