-Added development remarks in comment block.

applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd

@@ -48,12 +48,15 @@ USE bf_lib.bf_pkg.ALL;
 -- . The incpoming beamlets (3x 10GbE from fn_beamformer) are distributed among the 8 FPGAs per board; each FPGA correlates
 --   1/8th of the beamlets.
 -- Remarks:
+-- . The BG version (g_use_bg=TRUE) functionally works.
+-- . The 10G-input version (no BG) needs the DDR3 transpose in fn_beamformer to be in place.
+--   . Does the WPFB require SOP/EOP at its inputs? If so, we need to (re)set packet boundaries in the incoming stream of beamlet samples. --FIXME
+--   . fn_beamformer now outputs 176/256 beamlets but this might be increased to 192/256 (9.6Gbps) again as its 10G issue is solved.
 -- . URGENT:
 --   . We need 9b filter coefficients before we can synthesize! --FIXME
---   . How are we going to (re)map fn_beamformer's 176-word beamlet blocks onto the 128-word blocks wanted by the WPFB? --FIXME
+--     . Note: the 18b coeffieciens *do* fit and meet timing with only BG (without 10G RX stage).
 -- . Other:
 --   . Synthesis incl. mesh terminals went OK but used 96% of the logic resources.
---   . We need to add data buffers to monitor the incoming 3 (times 4 bf_units) streams (determine which bits are toggling etc). --FIXME
 --   . Keep an eye on the FIXME marks.
 
 ENTITY apertif_unb1_correlator IS