Correct bg_siso.ready

libraries/io/eth/src/vhdl/eth_tester_tx.vhd

@@ -92,6 +92,7 @@ ARCHITECTURE str OF eth_tester_tx IS
   SIGNAL bg_data                  : STD_LOGIC_VECTOR(c_octet_w-1 DOWNTO 0);
   SIGNAL bg_ctrl_hold             : t_diag_block_gen;
   SIGNAL bg_block_len             : NATURAL;
+  SIGNAL tx_packed_siso           : t_dp_siso;
   SIGNAL tx_packed_sosi           : t_dp_sosi;
   SIGNAL tx_packed_data           : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
   SIGNAL tx_fifo_sosi             : t_dp_sosi;
@@ -149,6 +150,10 @@ BEGIN
     out_siso_arr(0)       => bg_siso
   );
 
+  -- BG clock level flow control, needed when the dp_repack_data has to insert
+  -- empty octets into the last packed word.
+  bg_siso.ready <= tx_packed_siso.ready;
+
   -- BG block level flow control, needed in case BG settings result in eth bit
   -- rate > 1 Gbps, to avoid u_tx_fifo overflow.
   p_bg_siso_xon : PROCESS(st_clk)
@@ -173,6 +178,7 @@ BEGIN
   PORT MAP (
     rst              => st_rst,
     clk              => st_clk,
+    snk_out          => tx_packed_siso,
     snk_in           => bg_sosi,
     src_out          => tx_packed_sosi
   );