Unintentional commit, so revert back to revision 11326.

libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd

@@ -127,6 +127,8 @@ ARCHITECTURE str OF tr_10GbE IS
   SIGNAL tx_rst_n_arr                   : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
   SIGNAL rx_rst_n_arr                   : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
 
+  SIGNAL mm_rst_n                       : STD_LOGIC;
+
   SIGNAL reg_hdr_insert_mosi_arr        : t_mem_mosi_arr(g_nof_macs-1 DOWNTO 0);
   SIGNAL ram_hdr_insert_mosi_arr        : t_mem_mosi_arr(g_nof_macs-1 DOWNTO 0);
 
@@ -363,6 +365,8 @@ BEGIN
   tx_rst_n_arr <= NOT tx_rst_arr;
   rx_rst_n_arr <= NOT rx_rst_arr;
 
+  mm_rst_n <= NOT mm_rst;
+
   ---------------------------------------------------------------------------------------
   -- TX FIFO: dp_clk -> tx_clk
   ---------------------------------------------------------------------------------------
@@ -563,6 +567,7 @@ BEGIN
 
   ---------------------- Stratix iv -------------------------
 
+  gen_ip_stratixiv : if g_technology=c_tech_stratixiv generate
     gen_mac_10g : FOR i IN 0 TO sel_a_b(g_lpbk_sosi, 0, g_nof_macs)-1 GENERATE
 
       mac_10g_snk_out_arr(i).xon <= tx_rst_n_arr(i);
@@ -615,33 +620,6 @@ BEGIN
   
   		link_fault_status_xgmii_rx_data => OPEN 
       );
-      ENTITY mac_10g IS
-      GENERIC (
-        g_technology          : NATURAL := c_tech_select_default;
-        g_pre_header_padding  : BOOLEAN := FALSE
-      );
-      PORT (
-        -- MM
-        mm_clk           => mm_clk,
-        mm_rst           => mm_rst,
-        mac_mosi         : IN  t_mem_mosi;  -- MAC CSR = control status register
-        mac_miso         : OUT t_mem_miso;
-    
-        -- ST
-        tx_clk           : IN  STD_LOGIC;   -- 156.25 MHz local reference
-        tx_rst           : IN  STD_LOGIC;
-        tx_snk_in        : IN  t_dp_sosi;   -- 64 bit data
-        tx_snk_out       : OUT t_dp_siso; 
-        
-        rx_clk           : IN  STD_LOGIC;   -- 156.25 MHz from rx phy
-        rx_rst           : IN  STD_LOGIC;
-        rx_src_out       : OUT t_dp_sosi;   -- 64 bit data
-        rx_src_in        : IN  t_dp_siso; 
-        
-        -- XGMII
-        xgmii_tx_data    : OUT STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0);  -- 72 bit
-        xgmii_rx_data    : IN  STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0)   -- 72 bit
-      );
 
     END GENERATE;