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Commit e6509042 authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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svn cp and 'g_nof_streams' name change

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libraries/base/reorder/tb/tb_mmf_ss_parallel.vhd 0 → 100644
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View file @ e6509042
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
--
-- Purpose: Testbench for the ss_parallel unit.
-- To be used in conjunction with python script: ../python/tc_mmf_ss_parallel.py
--
-- The testbench can be used in two modes: auto-mode and non-auto-mode. The mode
-- is determined by the constant c_modelsim_start in the tc_mmf_ss_parallel.py script.
--
-- Usage in auto-mode (c_modelsim_start = 1 in python):
-- > Run python script in separate terminal: "python tc_mmf_ss_parallel.py --unb 0 --bn 0 --sim"
--
-- Usage in non-auto-mode (c_modelsim_start = 0 in python):
-- > as 5
-- > run -all
-- > Run python script in separate terminal: "python tc_mmf_ss_parallel.py --unb 0 --bn 0 --sim"
-- > Check the results of the python script.
-- > Stop the simulation manually in Modelsim by pressing the stop-button.
-- > Evalute the WAVE window.
LIBRARY IEEE, common_lib, mm_lib, diag_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_str_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
ENTITY tb_mmf_ss_parallel IS
GENERIC(
g_nof_inputs : NATURAL := 4;
g_nof_internals : NATURAL := 8;
g_nof_outputs : NATURAL := 8;
g_dsp_data_w : NATURAL := 16;
g_frame_size_in : NATURAL := 16;
g_frame_size_out : NATURAL := 16;
g_nof_frames : NATURAL := 1
);
END tb_mmf_ss_parallel;
ARCHITECTURE tb OF tb_mmf_ss_parallel IS
CONSTANT c_sim : BOOLEAN := TRUE;
----------------------------------------------------------------------------
-- Clocks and resets
----------------------------------------------------------------------------
CONSTANT c_mm_clk_period : TIME := 100 ps;
CONSTANT c_dp_clk_period : TIME := 5 ns;
CONSTANT c_sclk_period : TIME := 1250 ps;
CONSTANT c_dp_pps_period : NATURAL := 64;
SIGNAL dp_pps : STD_LOGIC;
SIGNAL mm_rst : STD_LOGIC := '1';
SIGNAL mm_clk : STD_LOGIC := '0';
SIGNAL dp_rst : STD_LOGIC;
SIGNAL dp_clk : STD_LOGIC := '0';
SIGNAL SCLK : STD_LOGIC := '0';
----------------------------------------------------------------------------
-- MM buses
----------------------------------------------------------------------------
SIGNAL reg_diag_bg_mosi : t_mem_mosi;
SIGNAL reg_diag_bg_miso : t_mem_miso;
SIGNAL ram_diag_bg_mosi : t_mem_mosi;
SIGNAL ram_diag_bg_miso : t_mem_miso;
SIGNAL ram_diag_data_buf_re_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_re_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_re_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_re_miso : t_mem_miso;
SIGNAL ram_diag_data_buf_im_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_im_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_im_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_im_miso : t_mem_miso;
SIGNAL ram_ss_reorder_in_mosi : t_mem_mosi;
SIGNAL ram_ss_reorder_in_miso : t_mem_miso;
SIGNAL ram_ss_reorder_out_mosi : t_mem_mosi;
SIGNAL ram_ss_reorder_out_miso : t_mem_miso;
SIGNAL ram_ss_ss_wide_mosi : t_mem_mosi;
SIGNAL ram_ss_ss_wide_miso : t_mem_miso;
----------------------------------------------------------------------------
-- Component declaration of mm_file
----------------------------------------------------------------------------
COMPONENT mm_file
GENERIC(
g_file_prefix : STRING;
g_update_on_change : BOOLEAN := FALSE
);
PORT (
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
mm_master_out : OUT t_mem_mosi;
mm_master_in : IN t_mem_miso
);
END COMPONENT;
-- Custom definitions of constants
CONSTANT c_bg_block_len : NATURAL := g_frame_size_in*g_nof_frames;
CONSTANT c_db_block_len : NATURAL := g_frame_size_out*g_nof_frames;
-- Configuration of the block generator:
CONSTANT c_bg_nof_output_streams : POSITIVE := g_nof_inputs;
CONSTANT c_bg_buf_dat_w : POSITIVE := c_nof_complex*g_dsp_data_w;
CONSTANT c_bg_buf_adr_w : POSITIVE := ceil_log2(c_bg_block_len);
CONSTANT c_bg_data_file_prefix : STRING := "UNUSED";
CONSTANT c_bg_data_file_index_arr : t_nat_natural_arr := array_init(0, g_nof_inputs, 1);
-- Configuration of the databuffers:
CONSTANT c_db_nof_streams : POSITIVE := g_nof_outputs;
CONSTANT c_db_data_w : POSITIVE := g_dsp_data_w;
CONSTANT c_db_buf_nof_data : POSITIVE := c_db_block_len;
CONSTANT c_db_buf_use_sync : BOOLEAN := FALSE;
CONSTANT c_db_data_type_re : t_diag_data_type_enum := e_real;
CONSTANT c_db_data_type_im : t_diag_data_type_enum := e_imag;
SIGNAL bg_siso_arr : t_dp_siso_arr(g_nof_inputs -1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy);
SIGNAL bg_sosi_arr : t_dp_sosi_arr(g_nof_inputs -1 DOWNTO 0);
SIGNAL out_sosi_arr : t_dp_sosi_arr(g_nof_outputs-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL out_siso_arr : t_dp_siso_arr(g_nof_outputs-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
BEGIN
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
mm_clk <= NOT mm_clk AFTER c_mm_clk_period/2;
mm_rst <= '1', '0' AFTER c_mm_clk_period*5;
SCLK <= NOT SCLK AFTER c_sclk_period/2;
dp_clk <= NOT dp_clk AFTER c_dp_clk_period/2;
dp_rst <= '1', '0' AFTER c_dp_clk_period*5;
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
----------------------------------------------------------------------------
-- MM buses
----------------------------------------------------------------------------
u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_BG")
PORT MAP(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_BG")
PORT MAP(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
u_mm_file_ram_diag_data_buf_re : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_REAL")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
u_mm_file_reg_diag_data_buf_re : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_REAL")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
u_mm_file_ram_diag_data_buf_im : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_IMAG")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
u_mm_file_reg_diag_data_buf_im : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_IMAG")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
u_mm_file_ram_ss_reorder_in : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "RAM_SS_REORDER_IN")
PORT MAP(mm_rst, mm_clk, ram_ss_reorder_in_mosi, ram_ss_reorder_in_miso);
u_mm_file_ram_ss_reorder_out : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "RAM_SS_REORDER_OUT")
PORT MAP(mm_rst, mm_clk, ram_ss_reorder_out_mosi, ram_ss_reorder_out_miso);
u_mm_file_ram_ss_ss_wide : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "RAM_SS_SS_WIDE")
PORT MAP(mm_rst, mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso);
----------------------------------------------------------------------------
-- Source: block generator
----------------------------------------------------------------------------
u_bg : ENTITY diag_lib.mms_diag_block_gen
GENERIC MAP(
g_nof_output_streams => c_bg_nof_output_streams,
g_buf_dat_w => c_bg_buf_dat_w,
g_buf_addr_w => c_bg_buf_adr_w,
g_file_index_arr => c_bg_data_file_index_arr,
g_file_name_prefix => c_bg_data_file_prefix
)
PORT MAP(
-- System
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
en_sync => dp_pps,
-- MM interface
reg_bg_ctrl_mosi => reg_diag_bg_mosi,
reg_bg_ctrl_miso => reg_diag_bg_miso,
ram_bg_data_mosi => ram_diag_bg_mosi,
ram_bg_data_miso => ram_diag_bg_miso,
-- ST interface
out_siso_arr => bg_siso_arr,
out_sosi_arr => bg_sosi_arr
);
----------------------------------------------------------------------------
-- DUT: Device Under Test
----------------------------------------------------------------------------
u_dut : ENTITY work.ss_parallel
GENERIC MAP(
g_nof_inputs => g_nof_inputs,
g_nof_internals => g_nof_internals,
g_nof_outputs => g_nof_outputs,
g_dsp_data_w => g_dsp_data_w,
g_frame_size_in => g_frame_size_in,
g_frame_size_out => g_frame_size_out
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
-- Memory Mapped
ram_ss_reorder_in_mosi => ram_ss_reorder_in_mosi,
ram_ss_reorder_in_miso => ram_ss_reorder_in_miso,
ram_ss_reorder_out_mosi => ram_ss_reorder_out_mosi,
ram_ss_reorder_out_miso => ram_ss_reorder_out_miso,
ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
-- Streaming
input_sosi_arr => bg_sosi_arr,
output_sosi_arr => out_sosi_arr,
output_siso_arr => out_siso_arr
);
----------------------------------------------------------------------------
-- Sink: data buffer real
----------------------------------------------------------------------------
u_data_buf_re : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
g_nof_streams => c_db_nof_streams,
g_data_type => c_db_data_type_re,
g_data_w => c_db_data_w,
g_buf_nof_data => c_db_buf_nof_data,
g_buf_use_sync => c_db_buf_use_sync
)
PORT MAP (
-- System
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
-- MM interface
ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
ram_data_buf_miso => ram_diag_data_buf_re_miso,
reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
reg_data_buf_miso => reg_diag_data_buf_re_miso,
-- ST interface
in_sync => OPEN,
in_sosi_arr => out_sosi_arr
);
----------------------------------------------------------------------------
-- Sink: data buffer imag
----------------------------------------------------------------------------
u_data_buf_im : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
g_nof_streams => c_db_nof_streams,
g_data_type => c_db_data_type_im,
g_data_w => c_db_data_w,
g_buf_nof_data => c_db_buf_nof_data,
g_buf_use_sync => c_db_buf_use_sync
)
PORT MAP (
-- System
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
-- MM interface
ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
ram_data_buf_miso => ram_diag_data_buf_im_miso,
reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
reg_data_buf_miso => reg_diag_data_buf_im_miso,
-- ST interface
in_sync => OPEN,
in_sosi_arr => out_sosi_arr
);
END tb;
libraries/base/reorder/tb/tb_mmf_ss_reorder.vhd 0 → 100644
+ 317
− 0
View file @ e6509042
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
--
-- Purpose: Testbench for the ss_reorder unit.
-- To be used in conjunction with python script: ../python/tc_mmf_ss_reorder.py
--
-- The testbench can be used in two modes: auto-mode and non-auto-mode. The mode
-- is determined by the constant c_modelsim_start in the tc_mmf_ss_reorder.py script.
--
-- Usage in auto-mode (c_modelsim_start = 1 in python):
-- > Run python script in separate terminal: "python tc_mmf_ss_reorder.py --unb 0 --bn 0 --sim"
--
-- Usage in non-auto-mode (c_modelsim_start = 0 in python):
-- > as 5
-- > run -all
-- > Run python script in separate terminal: "python tc_mmf_ss_reorder.py --unb 0 --bn 0 --sim"
-- > Check the results of the python script.
-- > Stop the simulation manually in Modelsim by pressing the stop-button.
-- > Evalute the WAVE window.
LIBRARY IEEE, common_lib, mm_lib, diag_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_str_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
ENTITY tb_mmf_ss_reorder IS
GENERIC(
g_nof_inputs : NATURAL := 8;
g_nof_outputs : NATURAL := 16;
g_dsp_data_w : NATURAL := 16;
g_frame_size : NATURAL := 16;
g_ram_init_file : STRING := "../../../src/data/select_buf"; -- or "UNUSED"
g_pipeline_in : NATURAL := 1; -- pipeline in_data
g_pipeline_in_m : NATURAL := 1; -- pipeline in_data for M-fold fan out
g_pipeline_out : NATURAL := 1; -- pipeline out_data
g_nof_frames : NATURAL := 1
);
END tb_mmf_ss_reorder;
ARCHITECTURE tb OF tb_mmf_ss_reorder IS
CONSTANT c_sim : BOOLEAN := TRUE;
----------------------------------------------------------------------------
-- Clocks and resets
----------------------------------------------------------------------------
CONSTANT c_mm_clk_period : TIME := 100 ps;
CONSTANT c_dp_clk_period : TIME := 5 ns;
CONSTANT c_sclk_period : TIME := 1250 ps;
CONSTANT c_dp_pps_period : NATURAL := 64;
SIGNAL dp_pps : STD_LOGIC;
SIGNAL mm_rst : STD_LOGIC := '1';
SIGNAL mm_clk : STD_LOGIC := '0';
SIGNAL dp_rst : STD_LOGIC;
SIGNAL dp_clk : STD_LOGIC := '0';
SIGNAL SCLK : STD_LOGIC := '0';
----------------------------------------------------------------------------
-- MM buses
----------------------------------------------------------------------------
SIGNAL reg_diag_bg_mosi : t_mem_mosi;
SIGNAL reg_diag_bg_miso : t_mem_miso;
SIGNAL ram_diag_bg_mosi : t_mem_mosi;
SIGNAL ram_diag_bg_miso : t_mem_miso;
SIGNAL ram_diag_data_buf_re_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_re_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_re_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_re_miso : t_mem_miso;
SIGNAL ram_diag_data_buf_im_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_im_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_im_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_im_miso : t_mem_miso;
SIGNAL ram_ss_reorder_mosi : t_mem_mosi;
SIGNAL ram_ss_reorder_miso : t_mem_miso;
----------------------------------------------------------------------------
-- Component declaration of mm_file
----------------------------------------------------------------------------
COMPONENT mm_file
GENERIC(
g_file_prefix : STRING;
g_update_on_change : BOOLEAN := FALSE
);
PORT (
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
mm_master_out : OUT t_mem_mosi;
mm_master_in : IN t_mem_miso
);
END COMPONENT;
-- Custom definitions of constants
CONSTANT c_bg_block_len : NATURAL := g_frame_size*g_nof_frames;
-- Configuration of the block generator:
CONSTANT c_bg_nof_output_streams : POSITIVE := g_nof_inputs;
CONSTANT c_bg_buf_dat_w : POSITIVE := c_nof_complex*g_dsp_data_w;
CONSTANT c_bg_buf_adr_w : POSITIVE := ceil_log2(c_bg_block_len);
CONSTANT c_bg_data_file_prefix : STRING := "UNUSED";
CONSTANT c_bg_data_file_index_arr : t_nat_natural_arr := array_init(0, g_nof_inputs, 1);
-- Configuration of the databuffers:
CONSTANT c_db_nof_streams : POSITIVE := g_nof_outputs;
CONSTANT c_db_data_w : POSITIVE := g_dsp_data_w;
CONSTANT c_db_buf_nof_data : POSITIVE := c_bg_block_len;
CONSTANT c_db_buf_use_sync : BOOLEAN := FALSE;
CONSTANT c_db_data_type_re : t_diag_data_type_enum := e_real;
CONSTANT c_db_data_type_im : t_diag_data_type_enum := e_imag;
-- Signal declarations to connect block generator, DUT and databuffers
SIGNAL bg_siso_arr : t_dp_siso_arr(g_nof_inputs -1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy);
SIGNAL bg_sosi_arr : t_dp_sosi_arr(g_nof_inputs -1 DOWNTO 0);
SIGNAL out_sosi_arr : t_dp_sosi_arr(g_nof_outputs-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL out_siso_arr : t_dp_siso_arr(g_nof_outputs-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
BEGIN
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
mm_clk <= NOT mm_clk AFTER c_mm_clk_period/2;
mm_rst <= '1', '0' AFTER c_mm_clk_period*5;
SCLK <= NOT SCLK AFTER c_sclk_period/2;
dp_clk <= NOT dp_clk AFTER c_dp_clk_period/2;
dp_rst <= '1', '0' AFTER c_dp_clk_period*5;
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
----------------------------------------------------------------------------
-- MM buses
----------------------------------------------------------------------------
u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_BG")
PORT MAP(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_BG")
PORT MAP(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
u_mm_file_ram_diag_data_buf_re : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_REAL")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
u_mm_file_reg_diag_data_buf_re : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_REAL")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
u_mm_file_ram_diag_data_buf_im : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "RAM_DIAG_DATA_BUFFER_IMAG")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
u_mm_file_reg_diag_data_buf_im : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "REG_DIAG_DATA_BUFFER_IMAG")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
u_mm_file_ram_ss_reorder : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "BN") & "RAM_SS_REORDER")
PORT MAP(mm_rst, mm_clk, ram_ss_reorder_mosi, ram_ss_reorder_miso);
----------------------------------------------------------------------------
-- Source: block generator
----------------------------------------------------------------------------
u_bg : ENTITY diag_lib.mms_diag_block_gen
GENERIC MAP(
g_nof_output_streams => c_bg_nof_output_streams,
g_buf_dat_w => c_bg_buf_dat_w,
g_buf_addr_w => c_bg_buf_adr_w,
g_file_index_arr => c_bg_data_file_index_arr,
g_file_name_prefix => c_bg_data_file_prefix
)
PORT MAP(
-- System
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
en_sync => dp_pps,
-- MM interface
reg_bg_ctrl_mosi => reg_diag_bg_mosi,
reg_bg_ctrl_miso => reg_diag_bg_miso,
ram_bg_data_mosi => ram_diag_bg_mosi,
ram_bg_data_miso => ram_diag_bg_miso,
-- ST interface
out_siso_arr => bg_siso_arr,
out_sosi_arr => bg_sosi_arr
);
----------------------------------------------------------------------------
-- DUT: Device Under Test
----------------------------------------------------------------------------
u_dut : ENTITY work.ss_reorder
GENERIC MAP(
g_nof_inputs => g_nof_inputs,
g_nof_outputs => g_nof_outputs,
g_dsp_data_w => g_dsp_data_w,
g_frame_size => g_frame_size,
g_ram_init_file => g_ram_init_file,
g_pipeline_in => g_pipeline_in,
g_pipeline_in_m => g_pipeline_in_m,
g_pipeline_out => g_pipeline_out
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
-- Memory Mapped
ram_ss_reorder_mosi => ram_ss_reorder_mosi,
ram_ss_reorder_miso => ram_ss_reorder_miso,
-- Streaming
input_sosi_arr => bg_sosi_arr,
output_sosi_arr => out_sosi_arr,
output_siso_arr => out_siso_arr
);
----------------------------------------------------------------------------
-- Sink: data buffer real
----------------------------------------------------------------------------
u_data_buf_re : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
g_nof_streams => c_db_nof_streams,
g_data_type => c_db_data_type_re,
g_data_w => c_db_data_w,
g_buf_nof_data => c_db_buf_nof_data,
g_buf_use_sync => c_db_buf_use_sync
)
PORT MAP (
-- System
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
-- MM interface
ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
ram_data_buf_miso => ram_diag_data_buf_re_miso,
reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
reg_data_buf_miso => reg_diag_data_buf_re_miso,
-- ST interface
in_sync => OPEN,
in_sosi_arr => out_sosi_arr
);
----------------------------------------------------------------------------
-- Sink: data buffer imag
----------------------------------------------------------------------------
u_data_buf_im : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
g_nof_streams => c_db_nof_streams,
g_data_type => c_db_data_type_im,
g_data_w => c_db_data_w,
g_buf_nof_data => c_db_buf_nof_data,
g_buf_use_sync => c_db_buf_use_sync
)
PORT MAP (
-- System
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
-- MM interface
ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
ram_data_buf_miso => ram_diag_data_buf_im_miso,
reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
reg_data_buf_miso => reg_diag_data_buf_im_miso,
-- ST interface
in_sync => OPEN,
in_sosi_arr => out_sosi_arr
);
END tb;
libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd
+ 1
− 1
View file @ e6509042
...@@ -245,7 +245,7 @@ BEGIN ...@@ -245,7 +245,7 @@ BEGIN
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
u_bg : ENTITY diag_lib.mms_diag_block_gen u_bg : ENTITY diag_lib.mms_diag_block_gen
GENERIC MAP( GENERIC MAP(
g_nof_output_streams => c_bg_nof_output_streams, g_nof_streams => c_bg_nof_output_streams,
g_buf_dat_w => c_bg_buf_dat_w, g_buf_dat_w => c_bg_buf_dat_w,
g_buf_addr_w => c_bg_buf_adr_w, g_buf_addr_w => c_bg_buf_adr_w,
g_file_index_arr => c_bg_data_file_index_arr, g_file_index_arr => c_bg_data_file_index_arr,
......
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