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Commit e63fd944 authored by Eric Kooistra's avatar Eric Kooistra
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Pipeline merged input sosi array to ease timing closure.

parent 3643f17a
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libraries/base/reorder/src/vhdl/reorder_transpose.vhd
+ 51
− 44
View file @ e63fd944
......@@ -148,11 +148,14 @@ ARCHITECTURE str OF reorder_transpose IS
CONSTANT c_data_w_ratio : POSITIVE := g_mem_dat_w/c_data_w;
SIGNAL sync_check_in_sosi : t_dp_sosi;
SIGNAL sync_check_in_siso : t_dp_siso := c_dp_siso_rdy;
SIGNAL merged_snk_in : t_dp_sosi;
SIGNAL merged_snk_out : t_dp_siso := c_dp_siso_rdy;
SIGNAL packet_merge_in_sosi : t_dp_sosi;
SIGNAL packet_merge_in_siso : t_dp_siso;
SIGNAL pipe_merged_snk_in : t_dp_sosi;
SIGNAL pipe_merged_snk_out : t_dp_siso := c_dp_siso_rdy;
SIGNAL sync_checked_src_out : t_dp_sosi;
SIGNAL sync_checked_src_in : t_dp_siso;
SIGNAL ss_in_sosi : t_dp_sosi;
SIGNAL ss_in_siso : t_dp_siso := c_dp_siso_rdy;
......@@ -168,7 +171,7 @@ ARCHITECTURE str OF reorder_transpose IS
SIGNAL i_to_mem_src_out : t_dp_sosi;
SIGNAL block_gen_out_sosi : t_dp_sosi;
SIGNAL pipeline_out_sosi : t_dp_sosi;
SIGNAL from_mem_out_sosi : t_dp_sosi;
SIGNAL sync_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
SIGNAL wr_req : STD_LOGIC;
......@@ -230,10 +233,10 @@ BEGIN
g_merge_in_complex : IF g_use_complex = TRUE GENERATE
PROCESS(snk_in_arr)
BEGIN
sync_check_in_sosi <= snk_in_arr(0);
merged_snk_in <= snk_in_arr(0);
FOR i IN 0 TO g_nof_streams-1 LOOP
sync_check_in_sosi.data((2*i+1)*g_in_dat_w-1 DOWNTO 2*i*g_in_dat_w) <= snk_in_arr(i).re(g_in_dat_w-1 DOWNTO 0);
sync_check_in_sosi.data((2*i+2)*g_in_dat_w-1 DOWNTO (2*i+1)*g_in_dat_w) <= snk_in_arr(i).im(g_in_dat_w-1 DOWNTO 0);
merged_snk_in.data((2*i+1)*g_in_dat_w-1 DOWNTO 2*i*g_in_dat_w) <= snk_in_arr(i).re(g_in_dat_w-1 DOWNTO 0);
merged_snk_in.data((2*i+2)*g_in_dat_w-1 DOWNTO (2*i+1)*g_in_dat_w) <= snk_in_arr(i).im(g_in_dat_w-1 DOWNTO 0);
END LOOP;
END PROCESS;
END GENERATE;
......@@ -241,20 +244,38 @@ BEGIN
g_merge_in_data : IF g_use_complex = FALSE GENERATE
PROCESS(snk_in_arr)
BEGIN
sync_check_in_sosi <= snk_in_arr(0);
merged_snk_in <= snk_in_arr(0);
FOR i IN 0 TO g_nof_streams-1 LOOP
sync_check_in_sosi.data((i+1)*g_in_dat_w-1 DOWNTO i*g_in_dat_w) <= snk_in_arr(i).data(g_in_dat_w-1 DOWNTO 0);
merged_snk_in.data((i+1)*g_in_dat_w-1 DOWNTO i*g_in_dat_w) <= snk_in_arr(i).data(g_in_dat_w-1 DOWNTO 0);
END LOOP;
END PROCESS;
END GENERATE;
g_siso : FOR J IN 0 TO g_nof_streams-1 GENERATE
snk_out_arr(J) <= sync_check_in_siso;
snk_out_arr(J) <= merged_snk_out;
END GENERATE;
-- Pipeline merged input
-- . to easy timing closure by decoupling the external memory interface and
-- the streaming input interface somewhat more (erko)
u_dp_pipeline_input : ENTITY dp_lib.dp_pipeline
GENERIC MAP(
g_pipeline => 1
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
-- ST sink
snk_out => merged_snk_out,
snk_in => merged_snk_in,
-- ST source
src_in => pipe_merged_snk_out,
src_out => pipe_merged_snk_in
);
u_sync_check_and_restore : ENTITY dp_lib.mms_dp_sync_checker
GENERIC MAP(
g_cross_clock_domain => TRUE,
g_nof_blk_per_sync => g_reorder_seq.nof_blocks
)
PORT MAP(
......@@ -262,27 +283,14 @@ BEGIN
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
snk_out => sync_check_in_siso,
snk_in => sync_check_in_sosi,
src_in => packet_merge_in_siso,
src_out => packet_merge_in_sosi,
snk_out => pipe_merged_snk_out,
snk_in => pipe_merged_snk_in,
src_in => sync_checked_src_in,
src_out => sync_checked_src_out,
reg_dp_sync_checker_mosi => reg_dp_sync_checker_mosi,
reg_dp_sync_checker_miso => reg_dp_sync_checker_miso
);
--u_sync_check_and_restore : ENTITY dp_lib.dp_sync_checker
--GENERIC MAP (
-- g_nof_blk_per_sync => g_reorder_seq.nof_blocks
--)
--PORT MAP (
-- dp_rst => dp_rst,
-- dp_clk => dp_clk,
-- snk_out => sync_check_in_siso,
-- snk_in => sync_check_in_sosi,
-- src_in => packet_merge_in_siso,
-- src_out => packet_merge_in_sosi
--);
gen_pre_transpose : IF g_ena_pre_transp = TRUE GENERATE
-- Packet merge is required for reorder_col.
u_dp_packet_merge : ENTITY dp_lib.dp_packet_merge
......@@ -293,8 +301,8 @@ BEGIN
rst => dp_rst,
clk => dp_clk,
snk_out => packet_merge_in_siso,
snk_in => packet_merge_in_sosi,
snk_out => sync_checked_src_in,
snk_in => sync_checked_src_out,
src_in => ss_in_siso,
src_out => ss_in_sosi
......@@ -330,8 +338,8 @@ BEGIN
END GENERATE;
gen_not_pre_transpose : IF g_ena_pre_transp = FALSE GENERATE
i_to_mem_src_out <= packet_merge_in_sosi;
packet_merge_in_siso <= to_mem_src_in;
i_to_mem_src_out <= sync_checked_src_out;
sync_checked_src_in <= to_mem_src_in;
END GENERATE;
-- Map original dvr interface signals to t_mem_ctlr_mosi/miso
......@@ -364,7 +372,7 @@ BEGIN
---------------------------------------------------------------
-- FIFO FOR SYNC-BSN
---------------------------------------------------------------
wr_req <= snk_in_arr(0).sync;
wr_req <= pipe_merged_snk_in.sync;
u_sync_bsn_fifo : ENTITY common_lib.common_fifo_sc
GENERIC MAP (
......@@ -409,7 +417,7 @@ BEGIN
);
-----------------------
-- Pipeline
-- Pipeline to match latency of dp_block_gen
-----------------------
u_dp_pipeline : ENTITY dp_lib.dp_pipeline
GENERIC MAP(
......@@ -423,7 +431,7 @@ BEGIN
snk_in => from_mem_snk_in,
-- ST source
src_in => OPEN,
src_out => pipeline_out_sosi
src_out => from_mem_out_sosi
);
--------------------
......@@ -444,7 +452,6 @@ BEGIN
snk_in => from_mem_snk_in,
-- Use incoming data to generate more data
src_in => c_dp_siso_rdy,
src_out => block_gen_out_sosi,
en => '1'
);
......@@ -452,13 +459,13 @@ BEGIN
from_mem_snk_out <= src_in_arr(0);
g_merge_out_complex : IF g_use_complex = TRUE GENERATE
gen_merge_out : PROCESS(block_gen_out_sosi, pipeline_out_sosi, sync_bsn)
gen_merge_out : PROCESS(block_gen_out_sosi, from_mem_out_sosi, sync_bsn)
BEGIN
FOR i IN 0 TO g_nof_streams-1 LOOP
merge_src_out_arr(i) <= block_gen_out_sosi;
merge_src_out_arr(i).valid <= pipeline_out_sosi.valid;
merge_src_out_arr(i).re <= RESIZE_DP_DSP_DATA(pipeline_out_sosi.data((2*i+1)*g_in_dat_w-1 DOWNTO 2*i*g_in_dat_w));
merge_src_out_arr(i).im <= RESIZE_DP_DSP_DATA(pipeline_out_sosi.data((2*i+2)*g_in_dat_w-1 DOWNTO (2*i+1)*g_in_dat_w));
merge_src_out_arr(i).valid <= from_mem_out_sosi.valid;
merge_src_out_arr(i).re <= RESIZE_DP_DSP_DATA(from_mem_out_sosi.data((2*i+1)*g_in_dat_w-1 DOWNTO 2*i*g_in_dat_w));
merge_src_out_arr(i).im <= RESIZE_DP_DSP_DATA(from_mem_out_sosi.data((2*i+2)*g_in_dat_w-1 DOWNTO (2*i+1)*g_in_dat_w));
IF (block_gen_out_sosi.sync = '1') THEN
merge_src_out_arr(i).bsn <= sync_bsn;
END IF;
......@@ -467,12 +474,12 @@ BEGIN
END GENERATE;
g_merge_out_data : IF g_use_complex = FALSE GENERATE
gen_merge_out : PROCESS(block_gen_out_sosi, pipeline_out_sosi)
gen_merge_out : PROCESS(block_gen_out_sosi, from_mem_out_sosi)
BEGIN
FOR i IN 0 TO g_nof_streams-1 LOOP
merge_src_out_arr(i) <= block_gen_out_sosi;
merge_src_out_arr(i).valid <= pipeline_out_sosi.valid;
merge_src_out_arr(i).data <= RESIZE_DP_DATA(pipeline_out_sosi.data((i+1)*g_in_dat_w-1 DOWNTO i*g_in_dat_w));
merge_src_out_arr(i).valid <= from_mem_out_sosi.valid;
merge_src_out_arr(i).data <= RESIZE_DP_DATA(from_mem_out_sosi.data((i+1)*g_in_dat_w-1 DOWNTO i*g_in_dat_w));
IF (block_gen_out_sosi.sync = '1') THEN
merge_src_out_arr(i).bsn <= sync_bsn;
END IF;
......
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