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Commit e5cf8886 authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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this design: 4xQSFP + 4xBack. Synthese ok

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boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+ 1
− 1
View file @ e5cf8886
...@@ -289,7 +289,7 @@ BEGIN ...@@ -289,7 +289,7 @@ BEGIN
-- Procedure that polls a sim control file that can be used to e.g. get -- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns -- the simulation time in ns
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat"); mmf_poll_sim_ctrl_file(mm_clk,c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
END GENERATE; END GENERATE;
......
boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+ 79
− 73
View file @ e5cf8886
...@@ -49,7 +49,7 @@ ENTITY unb2_test IS ...@@ -49,7 +49,7 @@ ENTITY unb2_test IS
g_factory_image : BOOLEAN := FALSE; g_factory_image : BOOLEAN := FALSE;
g_nof_streams_qsfp : NATURAL := 4;--c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w; g_nof_streams_qsfp : NATURAL := 4;--c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w;
g_nof_streams_ring : NATURAL := 0; --FIXME g_nof_streams_ring : NATURAL := 0; --FIXME
g_nof_streams_back : NATURAL := 0 --FIXME g_nof_streams_back : NATURAL := 4 --FIXME
); );
PORT ( PORT (
-- GENERAL -- GENERAL
...@@ -79,11 +79,11 @@ ENTITY unb2_test IS ...@@ -79,11 +79,11 @@ ENTITY unb2_test IS
BCK_REF_CLK : IN STD_LOGIC; -- BCK_REF_CLK : IN STD_LOGIC; --
-- back transceivers -- back transceivers
-- BCK_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 downto 0); BCK_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 downto 0);
-- BCK_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 downto 0); BCK_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 downto 0);
-- BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0); BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
-- BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0); BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
-- BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0); BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
-- ring transceivers -- ring transceivers
-- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0); -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
...@@ -97,8 +97,8 @@ ENTITY unb2_test IS ...@@ -97,8 +97,8 @@ ENTITY unb2_test IS
-- front transceivers -- front transceivers
QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- QSFP_1_RX : IN STD_LOGIC_VECTOR(1 downto 0); --c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- QSFP_1_TX : OUT STD_LOGIC_VECTOR(1 downto 0); --c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
...@@ -130,6 +130,7 @@ ARCHITECTURE str OF unb2_test IS ...@@ -130,6 +130,7 @@ ARCHITECTURE str OF unb2_test IS
CONSTANT c_use_10GbE : BOOLEAN := TRUE; --g_design_name = "unb2_test_10GbE"; CONSTANT c_use_10GbE : BOOLEAN := TRUE; --g_design_name = "unb2_test_10GbE";
CONSTANT g_nof_streams : NATURAL := (g_nof_streams_qsfp + g_nof_streams_ring + g_nof_streams_back); CONSTANT g_nof_streams : NATURAL := (g_nof_streams_qsfp + g_nof_streams_ring + g_nof_streams_back);
CONSTANT g_nof_qsfp_bus : NATURAL := ceil_div(g_nof_streams_qsfp,c_unb2_board_tr_qsfp.bus_w); CONSTANT g_nof_qsfp_bus : NATURAL := ceil_div(g_nof_streams_qsfp,c_unb2_board_tr_qsfp.bus_w);
CONSTANT g_nof_back_bus : NATURAL := ceil_div(g_nof_streams_back,c_unb2_board_tr_back.bus_w);
CONSTANT c_data_w : NATURAL := sel_a_b(c_use_lpbk, c_lpbk_data_w, -- Select correct c_data_w when one interface is used CONSTANT c_data_w : NATURAL := sel_a_b(c_use_lpbk, c_lpbk_data_w, -- Select correct c_data_w when one interface is used
sel_a_b(c_use_1GbE, c_eth_data_w, sel_a_b(c_use_1GbE, c_eth_data_w,
sel_a_b(c_use_10GbE, c_xgmii_data_w, 0))); sel_a_b(c_use_10GbE, c_xgmii_data_w, 0)));
...@@ -278,11 +279,13 @@ ARCHITECTURE str OF unb2_test IS ...@@ -278,11 +279,13 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL serial_10G_rx_qsfp_arr : STD_LOGIC_VECTOR(g_nof_streams_qsfp-1 DOWNTO 0); SIGNAL serial_10G_rx_qsfp_arr : STD_LOGIC_VECTOR(g_nof_streams_qsfp-1 DOWNTO 0);
SIGNAL serial_10G_tx_ring_arr : STD_LOGIC_VECTOR(g_nof_streams_ring-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL serial_10G_tx_ring_arr : STD_LOGIC_VECTOR(g_nof_streams_ring-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL serial_10G_rx_ring_arr : STD_LOGIC_VECTOR(g_nof_streams_ring-1 DOWNTO 0); SIGNAL serial_10G_rx_ring_arr : STD_LOGIC_VECTOR(g_nof_streams_ring-1 DOWNTO 0);
SIGNAL serial_10G_tx_back_arr : STD_LOGIC_VECTOR(g_nof_streams_back-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL serial_10G_tx_back_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL serial_10G_rx_back_arr : STD_LOGIC_VECTOR(g_nof_streams_back-1 DOWNTO 0); SIGNAL serial_10G_rx_back_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 DOWNTO 0);
SIGNAL reg_tr_10GbE_mosi : t_mem_mosi; SIGNAL reg_tr_10GbE_mosi : t_mem_mosi;
SIGNAL reg_tr_10GbE_miso : t_mem_miso; SIGNAL reg_tr_10GbE_miso : t_mem_miso;
SIGNAL reg_tr_10GbE_mosi2 : t_mem_mosi;
SIGNAL reg_tr_10GbE_miso2 : t_mem_miso;
SIGNAL reg_dp_ram_from_mm_mosi : t_mem_mosi; SIGNAL reg_dp_ram_from_mm_mosi : t_mem_mosi;
SIGNAL reg_dp_ram_from_mm_miso : t_mem_miso := c_mem_miso_rst; SIGNAL reg_dp_ram_from_mm_miso : t_mem_miso := c_mem_miso_rst;
...@@ -330,10 +333,6 @@ ARCHITECTURE str OF unb2_test IS ...@@ -330,10 +333,6 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL diag_data_buf_snk_out_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0); SIGNAL diag_data_buf_snk_out_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
--SIGNAL tmp_dp_offload_tx_src_out_arr : t_dp_sosi_arr(4*g_nof_streams-1 DOWNTO 0);
--SIGNAL tmp_dp_offload_tx_src_in_arr : t_dp_siso_arr(4*g_nof_streams-1 DOWNTO 0);
--SIGNAL tmp_dp_offload_rx_snk_in_arr : t_dp_sosi_arr(4*g_nof_streams-1 DOWNTO 0);
SIGNAL user_green_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0); SIGNAL user_green_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0);
SIGNAL user_red_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0); SIGNAL user_red_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0);
...@@ -343,7 +342,6 @@ ARCHITECTURE str OF unb2_test IS ...@@ -343,7 +342,6 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0); SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
BEGIN BEGIN
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
...@@ -808,43 +806,43 @@ BEGIN ...@@ -808,43 +806,43 @@ BEGIN
serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
); );
-- u_tr_10GbE_back: ENTITY unb2_board_lib.unb2_board_10gbe u_tr_10GbE_back: ENTITY unb2_board_lib.unb2_board_10gbe
-- GENERIC MAP ( GENERIC MAP (
-- g_technology => g_technology, g_technology => g_technology,
-- g_sim => g_sim, g_sim => g_sim,
-- g_sim_level => 1, g_sim_level => 1,
-- g_nof_macs => g_nof_streams_back, g_nof_macs => g_nof_streams_back,
-- g_tx_fifo_fill => c_def_10GbE_block_size, g_tx_fifo_fill => c_def_10GbE_block_size,
-- g_tx_fifo_size => c_def_10GbE_block_size*2 g_tx_fifo_size => c_def_10GbE_block_size*2
-- ) )
-- PORT MAP ( PORT MAP (
-- tr_ref_clk => SB_CLK, tr_ref_clk => SB_CLK,
--
-- -- MM interface
-- mm_rst => mm_rst,
-- mm_clk => mm_clk,
--
-- reg_mac_mosi => reg_tr_10GbE_mosi, -- FIXME use separate
-- reg_mac_miso => reg_tr_10GbE_miso,
--
-- -- DP interface
-- dp_rst => dp_rst,
-- dp_clk => dp_clk,
--
-- src_out_arr => dp_offload_rx_snk_in_arr((g_nof_streams_back-1) DOWNTO 0),
-- src_in_arr => dp_offload_rx_snk_out_arr((g_nof_streams_back-1) DOWNTO 0),
--
-- snk_out_arr => dp_offload_tx_src_in_arr((g_nof_streams_back-1) DOWNTO 0),
-- snk_in_arr => dp_offload_tx_src_out_arr((g_nof_streams_back-1) DOWNTO 0),
--
-- -- Serial IO
-- serial_tx_arr => i_serial_10G_tx_back_arr,
-- serial_rx_arr => i_serial_10G_rx_back_arr
-- );
-- MM interface
mm_rst => mm_rst,
mm_clk => mm_clk,
reg_mac_mosi => reg_tr_10GbE_mosi2, -- FIXME use separate
reg_mac_miso => reg_tr_10GbE_miso2,
gen_wires: FOR i IN 0 TO g_nof_streams_qsfp-1 GENERATE -- DP interface
dp_rst => dp_rst,
dp_clk => dp_clk,
src_out_arr => dp_offload_rx_snk_in_arr(g_nof_streams-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
src_in_arr => dp_offload_rx_snk_out_arr(g_nof_streams-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
snk_out_arr => dp_offload_tx_src_in_arr(g_nof_streams-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
snk_in_arr => dp_offload_tx_src_out_arr(g_nof_streams-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
-- Serial IO
serial_tx_arr => i_serial_10G_tx_back_arr,
serial_rx_arr => i_serial_10G_rx_back_arr
);
gen_qsfp_wires: FOR i IN 0 TO g_nof_streams_qsfp-1 GENERATE
serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i); serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
i_serial_10G_rx_qsfp_ring_arr(i) <= serial_10G_rx_qsfp_arr(i); i_serial_10G_rx_qsfp_ring_arr(i) <= serial_10G_rx_qsfp_arr(i);
END GENERATE; END GENERATE;
...@@ -859,6 +857,8 @@ BEGIN ...@@ -859,6 +857,8 @@ BEGIN
) )
PORT MAP ( PORT MAP (
--serial_tx_arr(g_nof_streams_qsfp-1 downto 0) => serial_10G_tx_qsfp_arr,
--serial_rx_arr(g_nof_streams_qsfp-1 downto 0) => serial_10G_rx_qsfp_arr,
serial_tx_arr => serial_10G_tx_qsfp_arr, serial_tx_arr => serial_10G_tx_qsfp_arr,
serial_rx_arr => serial_10G_rx_qsfp_arr, serial_rx_arr => serial_10G_rx_qsfp_arr,
...@@ -869,8 +869,11 @@ BEGIN ...@@ -869,8 +869,11 @@ BEGIN
-- front transceivers -- front transceivers
QSFP_RX(0) => QSFP_0_RX, QSFP_RX(0) => QSFP_0_RX,
QSFP_TX(0) => QSFP_0_TX, QSFP_TX(0) => QSFP_0_TX,
-- QSFP_RX(1) => QSFP_1_RX, -- QSFP_RX(1)(0) => QSFP_1_RX(0),
-- QSFP_TX(1) => QSFP_1_TX, -- QSFP_RX(1)(1) => QSFP_1_RX(1),
-- QSFP_TX(1)(0) => QSFP_1_TX(0),
-- QSFP_TX(1)(1) => QSFP_1_TX(1),
-- QSFP_RX(2) => QSFP_2_RX, -- QSFP_RX(2) => QSFP_2_RX,
-- QSFP_TX(2) => QSFP_2_TX, -- QSFP_TX(2) => QSFP_2_TX,
-- QSFP_RX(3) => QSFP_3_RX, -- QSFP_RX(3) => QSFP_3_RX,
...@@ -888,11 +891,7 @@ BEGIN ...@@ -888,11 +891,7 @@ BEGIN
); );
--tmp_dp_offload_tx_src_out_arr(0) <= dp_offload_tx_src_out_arr(0); u_front_led : ENTITY unb2_board_lib.unb2_board_qsfp_leds
--tmp_dp_offload_tx_src_in_arr(0) <= dp_offload_tx_src_in_arr(0);
--tmp_dp_offload_rx_snk_in_arr(0) <= dp_offload_rx_snk_in_arr(0);
u_front_led : ENTITY work.unb2_board_qsfp_leds
GENERIC MAP ( GENERIC MAP (
g_sim => g_sim, g_sim => g_sim,
g_factory_image => g_factory_image, g_factory_image => g_factory_image,
...@@ -907,6 +906,9 @@ BEGIN ...@@ -907,6 +906,9 @@ BEGIN
--pulse_ms => pulse_ms, --pulse_ms => pulse_ms,
--pulse_s => pulse_s, --pulse_s => pulse_s,
-- lane status -- lane status
--tx_siso_arr(g_nof_streams_qsfp-1 downto 0) => dp_offload_tx_src_in_arr(g_nof_streams_qsfp-1 DOWNTO 0),
--tx_sosi_arr(g_nof_streams_qsfp-1 downto 0) => dp_offload_tx_src_out_arr(g_nof_streams_qsfp-1 DOWNTO 0),
--rx_sosi_arr(g_nof_streams_qsfp-1 downto 0) => dp_offload_rx_snk_in_arr(g_nof_streams_qsfp-1 DOWNTO 0),
tx_siso_arr => dp_offload_tx_src_in_arr(g_nof_streams_qsfp-1 DOWNTO 0), tx_siso_arr => dp_offload_tx_src_in_arr(g_nof_streams_qsfp-1 DOWNTO 0),
tx_sosi_arr => dp_offload_tx_src_out_arr(g_nof_streams_qsfp-1 DOWNTO 0), tx_sosi_arr => dp_offload_tx_src_out_arr(g_nof_streams_qsfp-1 DOWNTO 0),
rx_sosi_arr => dp_offload_rx_snk_in_arr(g_nof_streams_qsfp-1 DOWNTO 0), rx_sosi_arr => dp_offload_rx_snk_in_arr(g_nof_streams_qsfp-1 DOWNTO 0),
...@@ -915,24 +917,28 @@ BEGIN ...@@ -915,24 +917,28 @@ BEGIN
red_led_arr => user_red_led_arr(g_nof_qsfp_bus-1 DOWNTO 0) red_led_arr => user_red_led_arr(g_nof_qsfp_bus-1 DOWNTO 0)
); );
gen_back_wires: FOR i IN 0 TO g_nof_streams_back-1 GENERATE
serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back_arr(i);
i_serial_10G_rx_back_arr(i) <= serial_10G_rx_back_arr(i);
END GENERATE;
-- u_back_io : ENTITY unb2_board_lib.unb2_board_back_io u_back_io : ENTITY unb2_board_lib.unb2_board_back_io
-- GENERIC MAP ( GENERIC MAP (
-- g_nof_back_io => g_nof_streams_back g_nof_back_bus => g_nof_back_bus
-- ) )
-- PORT MAP ( PORT MAP (
-- serial_tx_arr => serial_10G_tx_back_arr, serial_tx_arr => serial_10G_tx_back_arr,
-- serial_rx_arr => serial_10G_rx_back_arr, serial_rx_arr => serial_10G_rx_back_arr,
--
-- -- Serial I/O -- Serial I/O
-- -- back transceivers -- back transceivers
-- BCK_RX => BCK_RX, BCK_RX(0) => BCK_RX,--(g_nof_streams_back-1 downto 0),
-- BCK_TX => BCK_TX, BCK_TX(0) => BCK_TX,--(g_nof_streams_back-1 downto 0),
--
-- BCK_SDA => BCK_SDA, BCK_SDA => BCK_SDA,
-- BCK_SCL => BCK_SCL, BCK_SCL => BCK_SCL,
-- BCK_ERR => BCK_ERR BCK_ERR => BCK_ERR
-- ); );
-- --
-- u_ring_io : ENTITY unb2_board_lib.unb2_board_ring_io -- u_ring_io : ENTITY unb2_board_lib.unb2_board_ring_io
-- GENERIC MAP ( -- GENERIC MAP (
......
boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
+ 7
− 2
View file @ e5cf8886
...@@ -104,7 +104,9 @@ ARCHITECTURE tb OF tb_unb2_test IS ...@@ -104,7 +104,9 @@ ARCHITECTURE tb OF tb_unb2_test IS
--SIGNAL si_fn_lpbk_1 : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); --SIGNAL si_fn_lpbk_1 : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
--SIGNAL si_fn_lpbk_2 : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); --SIGNAL si_fn_lpbk_2 : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
--SIGNAL si_fn_lpbk_3 : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); --SIGNAL si_fn_lpbk_3 : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL si_lpbk_0 : STD_LOGIC_VECTOR(0 DOWNTO 0); SIGNAL si_lpbk_0 : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0);
SIGNAL si_lpbk_1 : STD_LOGIC_VECTOR(3 DOWNTO 0);
-- Model I2C sensor slaves as on the UniBoard -- Model I2C sensor slaves as on the UniBoard
...@@ -189,7 +191,10 @@ BEGIN ...@@ -189,7 +191,10 @@ BEGIN
-- Serial I/O -- Serial I/O
QSFP_0_TX => si_lpbk_0, QSFP_0_TX => si_lpbk_0,
QSFP_0_RX => si_lpbk_0 QSFP_0_RX => si_lpbk_0,
BCK_TX => si_lpbk_1,
BCK_RX => si_lpbk_1
); );
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
......
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