Issue tx_snk_out XON when Tx PHY is ready and XGMII is ok

libraries/technology/eth_10g/tech_eth_10g_arria10.vhd

@@ -41,11 +41,13 @@ USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE common_lib.common_interface_layers_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
+USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;
 
 ENTITY tech_eth_10g_arria10 IS
   GENERIC (
     g_sim                 : BOOLEAN := FALSE;
     g_nof_channels        : NATURAL := 1;
+    g_link_status_check   : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "11";
     g_pre_header_padding  : BOOLEAN := FALSE
   );
   PORT (
@@ -80,13 +82,33 @@ END tech_eth_10g_arria10;
 
 ARCHITECTURE str OF tech_eth_10g_arria10 IS
 
+  -- XON control
+  SIGNAL mac_snk_out_arr       : t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+  
   -- XGMII
-  SIGNAL xgmii_tx_dc_arr    : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);  -- 72 bit
-  SIGNAL xgmii_rx_dc_arr    : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);  -- 72 bit
+  SIGNAL xgmii_link_status_arr : t_tech_mac_10g_xgmii_status_arr(g_nof_channels-1 DOWNTO 0);  -- 2 bit, from MAC_10g
+  SIGNAL xgmii_tx_ready_arr    : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);                 -- 1 bit, from PHY 10gbase_r
+  SIGNAL xgmii_tx_dc_arr       : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);    -- 72 bit
+  SIGNAL xgmii_rx_dc_arr       : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);    -- 72 bit
 
 BEGIN
                    
   gen_mac : FOR I IN 0 TO g_nof_channels-1 GENERATE
+  
+    tx_snk_out_arr(I).ready <= mac_snk_out_arr(I).ready;  -- pass on MAC cycle accurate backpressure
+    
+    p_xon_flow_control : PROCESS(clk_156)
+      VARIABLE v_xgmii_link_status : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0);
+    BEGIN
+      IF rising_edge(clk_156) THEN
+        tx_snk_out_arr(I).xon <= '0';
+        v_xgmii_link_status := xgmii_link_status_arr(I) AND g_link_status_check;  -- use mask to check Tx, Rx, both or none. 
+        IF xgmii_tx_ready_arr(I)='1' AND v_xgmii_link_status="00" THEN
+          tx_snk_out_arr(I).xon <= '1';  -- XON when Tx PHY is ready and XGMII is ok
+        END IF;
+      END IF;
+    END PROCESS;
+    
     u_tech_mac_10g : ENTITY tech_mac_10g_lib.tech_mac_10g
     GENERIC MAP (
       g_technology          => c_tech_arria10,
@@ -94,27 +116,28 @@ BEGIN
     )
     PORT MAP (
       -- MM
-      mm_clk           => mm_clk,
-      mm_rst           => mm_rst,
-      csr_mosi         => mac_mosi_arr(I),
-      csr_miso         => mac_miso_arr(I),
+      mm_clk            => mm_clk,
+      mm_rst            => mm_rst,
+      csr_mosi          => mac_mosi_arr(I),
+      csr_miso          => mac_miso_arr(I),
   
       -- ST
-      tx_clk_312       => clk_312,
-      tx_clk_156       => clk_156,
-      tx_rst           => rst_156,
-      tx_snk_in        => tx_snk_in_arr(I),   -- 64 bit data
-      tx_snk_out       => tx_snk_out_arr(I),
+      tx_clk_312        => clk_312,
+      tx_clk_156        => clk_156,
+      tx_rst            => rst_156,
+      tx_snk_in         => tx_snk_in_arr(I),   -- 64 bit data
+      tx_snk_out        => mac_snk_out_arr(I),
       
-      rx_clk_312       => clk_312,
-      rx_clk_156       => clk_156,
-      rx_rst           => rst_156,
-      rx_src_out       => rx_src_out_arr(I),  -- 64 bit data
-      rx_src_in        => rx_src_in_arr(I),
+      rx_clk_312        => clk_312,
+      rx_clk_156        => clk_156,
+      rx_rst            => rst_156,
+      rx_src_out        => rx_src_out_arr(I),  -- 64 bit data
+      rx_src_in         => rx_src_in_arr(I),
             
       -- XGMII
-      xgmii_tx_data    => xgmii_tx_dc_arr(I),
-      xgmii_rx_data    => xgmii_rx_dc_arr(I)
+      xgmii_link_status => xgmii_link_status_arr(I),
+      xgmii_tx_data     => xgmii_tx_dc_arr(I),
+      xgmii_rx_data     => xgmii_rx_dc_arr(I)
     );
   END GENERATE;
   
@@ -133,6 +156,7 @@ BEGIN
     rst_156            => rst_156,
 
     -- XGMII interface
+    xgmii_tx_ready_arr => xgmii_tx_ready_arr,
     xgmii_tx_dc_arr    => xgmii_tx_dc_arr,
     xgmii_rx_dc_arr    => xgmii_rx_dc_arr,