Added support for testing MB_I and MB_II in parallel.

boards/uniboard2/designs/unb2_test/tb/python/tc_unb2_test_ddr.py

@@ -27,13 +27,15 @@ Description:
   
 Usage:
 
-  1) Load and run tb_unb2_test_ddr simulation.
-  2) > python tc_unb2_test_ddr.py --sim --unb 0 --gn 3 -v 5
+  1) Load and run simulation of tb_unb2_test_ddr_MB_I, tb_unb2_test_ddr_MB_II or tb_unb2_test_ddr_MB_I_II
+  2) > python tc_unb2_test_ddr.py --sim --unb 0 --gn 3 -v 5 -s I --rep 1
+  3) After about 160 us cal_ok
   
 """
 
 ###############################################################################
 # System imports
+import sys
 import test_case
 import node_io
 import pi_diag_tx_seq
@@ -53,7 +55,7 @@ from pi_common import *
 tc = test_case.Testcase('TB - ', '')
 tc.set_result('PASSED')
 tc.append_log(3, '>>>')
-tc.append_log(1, '>>> Title : Test case for the unb1_ddr3 design on %s' % tc.unb_nodes_string())
+tc.append_log(1, '>>> Title : Test case for the unb2_test_ddr design with MB = %s on %s' % (tc.gpString, tc.unb_nodes_string()))
 tc.append_log(3, '>>>')
 tc.append_log(3, '')
     
@@ -61,14 +63,21 @@ tc.append_log(3, '')
 io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
     
 # Create instances for the periperals
-c_nof_streams = 1
+mb_list = tc.gpString.split(',');
+
+io_ddr     = dict()
+tx_seq_ddr = dict()
+rx_seq_ddr = dict()
+rx_db_ddr  = dict()
+for mb in mb_list:
+    if mb=='I' or mb=='II':
+        io_ddr[mb]     = pi_io_ddr.PiIoDdr(tc, io, inst_name="MB_"+mb, nof_inst=1)
+        tx_seq_ddr[mb] = pi_diag_tx_seq.PiDiagTxSeq(tc, io, inst_name="DDR_MB_"+mb, nof_inst=1)
+        rx_seq_ddr[mb] = pi_diag_rx_seq.PiDiagRxSeq(tc, io, inst_name="DDR_MB_"+mb, nof_inst=1)
+        rx_db_ddr[mb]  = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, instanceName="DDR_MB_"+mb, nofStreams=1)
+    else:
+        sys.exit("Wrong type of MB argument, must be -s I or -s II or -s I,II")
 
-tx_seq = pi_diag_tx_seq.PiDiagTxSeq(tc, io, inst_name="DDR", nof_inst=c_nof_streams)
-rx_seq = pi_diag_rx_seq.PiDiagRxSeq(tc, io, inst_name="DDR", nof_inst=c_nof_streams)
-rx_db  = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, instanceName="DDR", nofStreams=c_nof_streams)
-
-# Create object for DDR register map
-ddr = pi_io_ddr.PiIoDdr(tc, io, nof_inst = 1)
 
 ##################################################################################################################
 # Test
@@ -77,58 +86,63 @@ ddr = pi_io_ddr.PiIoDdr(tc, io, nof_inst = 1)
 io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
 
 # Control defaults
-nof_mon = 2
-start_address = 0
+nof_mon = 5
+start_address = 7
 nof_words = 100
 
 for rep in range(tc.repeat):
     tc.append_log(5, '')
     tc.append_log(3, '>>> Rep-%d' % rep)
     
+    # Use separate for-loop sections to access the MB I and MB II more simultaneously instead of sequentially
+    for mb in mb_list:
         # Initialization
-    tx_seq.write_disable(vLevel=5)
-    rx_seq.write_disable(vLevel=5)
+        tx_seq_ddr[mb].write_disable(vLevel=5)
+        rx_seq_ddr[mb].write_disable(vLevel=5)
         
         # Wait for the DDR memory to become available    
-    do_until_eq(ddr.read_init_done, ms_retry=3000, val=1, s_timeout=3600)        
+        do_until_eq(io_ddr[mb].read_init_done, ms_retry=3000, val=1, s_timeout=3600)        
         
+    for mb in mb_list:
         # Flush Tx FIFO
-    ddr.write_flush_pulse(vLevel=5)
+        io_ddr[mb].write_flush_pulse(vLevel=5)
         io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
         
         # Set DDR controller in write mode and start writing
-    ddr.write_set_address(data=start_address, vLevel=5)
-    ddr.write_access_size(data=nof_words, vLevel=5)
-    ddr.write_mode_write(vLevel=5)
-    ddr.write_begin_access(vLevel=5)
+        io_ddr[mb].write_set_address(data=start_address, vLevel=5)
+        io_ddr[mb].write_access_size(data=nof_words, vLevel=5)
+        io_ddr[mb].write_mode_write(vLevel=5)
+        io_ddr[mb].write_begin_access(vLevel=5)
         
         # Tx sequence start
-    tx_seq.write_enable_cntr(vLevel=5)
+        tx_seq_ddr[mb].write_enable_cntr(vLevel=5)
         
         # Tx sequence monitor
         for mon in range(nof_mon):
             io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
-        tx_seq.read_cnt(vLevel=5)
+            tx_seq_ddr[mb].read_cnt(vLevel=5)
         
+    for mb in mb_list:
         # Wait until controller write access is done
-    do_until_eq(ddr.read_done, ms_retry=3000, val=1, s_timeout=3600)        
+        do_until_eq(io_ddr[mb].read_done, ms_retry=3000, val=1, s_timeout=3600)        
         
         # Rx sequence start
-    rx_seq.write_enable_cntr(vLevel=5)
+        rx_seq_ddr[mb].write_enable_cntr(vLevel=5)
         
         # Set DDR3 controller in read mode and start reading
-    ddr.write_mode_read(vLevel=5)
-    ddr.write_begin_access(vLevel=5)
+        io_ddr[mb].write_mode_read(vLevel=5)
+        io_ddr[mb].write_begin_access(vLevel=5)
         
         # Rx sequence monitor
         for mon in range(nof_mon):
             io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
-        rx_seq.read_cnt(vLevel=5)
+            rx_seq_ddr[mb].read_cnt(vLevel=5)
         
+    for mb in mb_list:
         # Wait until controller read access is done
-    do_until_eq(ddr.read_done, ms_retry=3000, val=1, s_timeout=3600)        
+        do_until_eq(io_ddr[mb].read_done, ms_retry=3000, val=1, s_timeout=3600)        
         
-    rx_seq.read_result(vLevel=5)
+        rx_seq_ddr[mb].read_result(vLevel=5)
         
 
 # End