processed review comments

applications/lofar2/designs/lofar2_unb2b_ring/hdllib.cfg

@@ -13,7 +13,7 @@ hdl_lib_include_ip =
 synth_files =
     src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
     src/vhdl/lofar2_unb2b_ring_pkg.vhd
-    src/vhdl/mmm_lofar2_unb2b_ring.vhd
+    src/vhdl/mmc_lofar2_unb2b_ring.vhd
     src/vhdl/lofar2_unb2b_ring.vhd
     
 test_bench_files = 

applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_full.vhd → applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd

@@ -24,6 +24,9 @@
 -- Description:
 --   Unb2b version for lab testing
 --   Contains ring design with 1 lane.
+-- Remark:
+--   Note that the amount of transceivers support 2 lanes, one even and one odd.
+--   However only 1 ring_lane.vhd component is instantiated with lane index 0 (even).
 
 
 LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_ring_lib;

applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd

@@ -21,9 +21,9 @@
 -------------------------------------------------------------------------------
 -- Author : R vd Walle
 -- Purpose:  
---   Core design for Lofar2 SDP station
+--   Design for Lofar2 Ring interface testing.
 -- Description:
---   Unb2b version for lab testing, using generic sdp_station.vhd for LOFAR2 SDP application.
+--   Unb2b version for lab testing, see https://support.astron.nl/confluence/x/jyu7Ag.
 -------------------------------------------------------------------------------
 
 LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, tr_10gbe_lib, eth_lib, ring_lib;
@@ -124,8 +124,8 @@ ARCHITECTURE str OF lofar2_unb2b_ring IS
   CONSTANT c_nof_streams_ring       : NATURAL := c_ring_bus_w*c_nof_ring_bus; --c_unb2b_board_tr_ring.bus_w*c_nof_ring_bus; -- 8
 
   -- 10GbE
-  CONSTANT c_nof_even_lanes         : NATURAL := ceil_div(c_nof_lanes, 2);
-  CONSTANT c_nof_odd_lanes          : NATURAL := c_nof_lanes / 2;
+  CONSTANT c_nof_even_lanes         : NATURAL := ceil_div(c_nof_lanes, 2); -- nof lanes transmitting in positive direction. Using ceil_div as c_nof_lanes might be odd.
+  CONSTANT c_nof_odd_lanes          : NATURAL := c_nof_lanes / 2; -- nof lanes transmitting in negative direction.
   CONSTANT c_nof_mac                : NATURAL := 3 * c_nof_even_lanes; -- must match one of the MAC IP variations, e.g. 3, 12, 24, 48
 
   CONSTANT c_lane_data_w               : NATURAL := 64; 
@@ -470,9 +470,9 @@ BEGIN
   );
 
   -----------------------------------------------------------------------------
-  -- MM master
+  -- MM controller
   -----------------------------------------------------------------------------
-  u_mmm : ENTITY work.mmm_lofar2_unb2b_ring
+  u_mmc : ENTITY work.mmc_lofar2_unb2b_ring
   GENERIC MAP (
     g_sim         => g_sim,
     g_sim_unb_nr  => g_sim_unb_nr,
@@ -616,7 +616,7 @@ BEGIN
   -----------------------------------------------------------------------------
   -- MMP diag_block_gen
   -----------------------------------------------------------------------------
-  u_mms_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen
+  u_mmp_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen
   PORT MAP (
     mm_rst  => mm_rst,
     mm_clk  => mm_clk,
@@ -636,7 +636,7 @@ BEGIN
   -----------------------------------------------------------------------------
   -- MMP dp_xonoff from_lane_sosi
   -----------------------------------------------------------------------------
-  u_mms_dp_xonoff_lane : ENTITY dp_lib.mms_dp_xonoff
+  u_mmp_dp_xonoff_lane : ENTITY dp_lib.mms_dp_xonoff
   GENERIC MAP (
     g_nof_streams   => c_nof_lanes,
     g_default_value => '0'
@@ -665,7 +665,7 @@ BEGIN
     dp_xonoff_local_snk_in_arr(I) <= local_sosi; -- copy local sosi to all lanes
   END GENERATE;  
 
-  u_mms_dp_xonoff_local : ENTITY dp_lib.mms_dp_xonoff
+  u_mmp_dp_xonoff_local : ENTITY dp_lib.mms_dp_xonoff
   GENERIC MAP (
     g_nof_streams   => c_nof_lanes,
     g_default_value => '0'
@@ -904,6 +904,8 @@ BEGIN
   -----------------------------------------------------------------------------
   -- Seperate serial tx/rx array 
   -----------------------------------------------------------------------------  
+  -- Seperating the one large serial tx/rx array from tr_10GbE to the 3 port arrays:
+  -- QSFP port, RING_0 port and RING_1 port.
   gen_seperate: FOR I IN 0 TO c_nof_even_lanes-1 GENERATE 
     -- QSFP_TX
     unb2_board_front_io_serial_tx_arr(I) <= tr_10gbe_serial_tx_arr(3*I); 

applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmm_lofar2_unb2b_ring.vhd → applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd

@@ -30,7 +30,7 @@ USE mm_lib.mm_file_unb_pkg.ALL;
 USE work.qsys_lofar2_unb2b_ring_pkg.ALL;
 USE lofar2_sdp_lib.sdp_pkg.ALL;
 
-ENTITY mmm_lofar2_unb2b_ring IS
+ENTITY mmc_lofar2_unb2b_ring IS
   GENERIC (
     g_sim         : BOOLEAN := FALSE; --FALSE: use QSYS; TRUE: use mm_file I/O
     g_sim_unb_nr  : NATURAL := 0;
@@ -147,9 +147,9 @@ ENTITY mmm_lofar2_unb2b_ring IS
     ram_scrap_cipo                         : IN  t_mem_cipo
 
   );
-END mmm_lofar2_unb2b_ring;
+END mmc_lofar2_unb2b_ring;
 
-ARCHITECTURE str OF mmm_lofar2_unb2b_ring IS
+ARCHITECTURE str OF mmc_lofar2_unb2b_ring IS
 
   CONSTANT c_sim_node_nr   : NATURAL := g_sim_node_nr;
   CONSTANT c_sim_node_type : STRING(1 TO 2):= "FN";

libraries/base/ring/src/vhdl/ring_info_reg.vhd

-