removed unused jesd204b_reset signal.

applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd

@@ -145,14 +145,13 @@ ARCHITECTURE str OF node_sdp_adc_input_and_timing IS
   SIGNAL mm_rst_internal            : STD_LOGIC; 
   SIGNAL mm_jesd_ctrl_reg           : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
   SIGNAL jesd204b_disable_arr       : STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0);
-  SIGNAL jesd204b_reset             : STD_LOGIC;
 
 BEGIN
 
-  -- The node AIT is reset at power up by mm_rst and under software control by jesd204b_reset.
+  -- The node AIT is reset at power up by mm_rst and under software control by jesd204b_disable_arr.
   -- The mm_rst internal will cause a reset on the rx_rst by the reset sequencer in the u_jesd204b.
-  -- The MM jesd204b_reset is intended for node AIT resynchronisation tests of the u_jesd204b.
-  -- The MM jesd204b_reset should not be applied in an SDP application, because this will cause
+  -- The MM jesd204b_disable_arr is intended for node AIT resynchronisation tests of the u_jesd204b.
+  -- The MM jesd204b_disable_arr should not be applied in an SDP application, because this will cause
   -- a disturbance in the block timing of the out_sosi_arr(i).sync,bsn,sop,eop. The other logic
   -- in an SDP application assumes that the block timing of the out_sosi_arr(i) only contains
   -- complete blocks, so from sop to eop.