-Commented out tb_tb_uth_terminals.vhd from regression test as it is taking too long.

libraries/base/uth/hdllib.cfg

@@ -25,7 +25,7 @@ test_bench_files =
 regression_test_vhdl = 
     tb/vhdl/tb_tb_uth.vhd
     tb/vhdl/tb_tb_uth_dp_packet.vhd
-    tb/vhdl/tb_tb_uth_terminals.vhd
+#    tb/vhdl/tb_tb_uth_terminals.vhd
 
     
 [modelsim_project_file]