fpga temp sensor for unb2 in progress...

boards/uniboard2/libraries/unb2_board/hdllib.cfg

 hdl_lib_name = unb2_board
 hdl_library_clause_name = unb2_board_lib
-hdl_lib_uses_synth = common dp diag uth ppsh i2c tr_nonbonded eth remu technology tech_clkbuf tech_pll tech_fractional_pll epcs tr_10GbE
+hdl_lib_uses_synth = common dp diag uth ppsh i2c tr_nonbonded eth remu technology tech_clkbuf tech_pll tech_fractional_pll epcs tr_10GbE fpga_temp_sens
 hdl_lib_uses_sim = 
 
 hdl_lib_technology = ip_arria10
@@ -19,7 +19,9 @@ synth_files =
     src/vhdl/unb2_board_sens_ctrl.vhd
     src/vhdl/unb2_board_sens.vhd
     src/vhdl/unb2_board_sens_reg.vhd
+    src/vhdl/unb2_fpga_sens_reg.vhd
     src/vhdl/mms_unb2_board_sens.vhd
+    src/vhdl/mms_unb2_fpga_sens.vhd
     src/vhdl/unb2_board_wdi_reg.vhd
     src/vhdl/unb2_board_qsfp_leds.vhd
     src/vhdl/ctrl_unb2_board.vhd

boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd

@@ -180,6 +180,9 @@ ENTITY ctrl_unb2_board IS
     -- UniBoard I2C sensors
     reg_unb_sens_mosi      : IN  t_mem_mosi := c_mem_mosi_rst;
     reg_unb_sens_miso      : OUT t_mem_miso;
+
+    reg_fpga_sens_mosi     : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_fpga_sens_miso     : OUT t_mem_miso;
     
     -- PPSH
     reg_ppsh_mosi          : IN  t_mem_mosi := c_mem_mosi_rst;
@@ -661,12 +664,32 @@ BEGIN
     
     -- i2c bus
     scl       => SENS_SC,
-    sda       => SENS_SD,
+    sda       => SENS_SD
 
+    -- Temperature alarm
+    --temp_alarm => temp_alarm
+  );
+
+  u_mms_unb2_fpga_sens : ENTITY work.mms_unb2_fpga_sens
+  GENERIC MAP (
+    g_sim        => g_sim,
+    g_technology => g_technology,
+    g_temp_high  => g_fpga_temp_high
+  )
+  PORT MAP (
+    -- Clocks and reset
+    mm_rst    => i_mm_rst,
+    mm_clk    => i_mm_clk,
+    mm_start  => mm_board_sens_start,
+    
+    -- Memory-mapped clock domain
+    reg_mosi  => reg_fpga_sens_mosi,
+    reg_miso  => reg_fpga_sens_miso,
+    
     -- Temperature alarm
     temp_alarm => temp_alarm
   );
-  
+
 
   ------------------------------------------------------------------------------
   -- Ethernet 1GbE
@@ -712,7 +735,7 @@ BEGIN
   END GENERATE;
 
 
-  gen_eth: IF g_sim = FALSE GENERATE
+--  gen_eth: IF g_sim = FALSE GENERATE
     u_eth : ENTITY eth_lib.eth
     GENERIC MAP (
       g_technology         => g_technology,
@@ -750,6 +773,6 @@ BEGIN
       -- LED interface
       tse_led           => eth1g_led
     );
-  END GENERATE;
+--  END GENERATE;
   
 END str;

boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012-2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose : MMS for unb2_fpga_sens
+-- Description: See unb2_fpga_sens.vhd
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+
+
+ENTITY mms_unb2_fpga_sens IS
+  GENERIC (
+    g_sim             : BOOLEAN := FALSE;
+    g_technology      : NATURAL;
+    g_temp_high       : NATURAL := 85
+  );
+  PORT (
+    -- Clocks and reset
+    mm_rst            : IN  STD_LOGIC;  -- reset synchronous with mm_clk
+    mm_clk            : IN  STD_LOGIC;  -- memory-mapped bus clock
+    mm_start          : IN  STD_LOGIC;
+    
+    -- Memory-mapped clock domain
+    reg_mosi          : IN  t_mem_mosi := c_mem_mosi_rst;  -- actual ranges defined by c_mm_reg
+    reg_miso          : OUT t_mem_miso;                    -- actual ranges defined by c_mm_reg
+    
+    -- Temperature alarm output
+    temp_alarm        : OUT STD_LOGIC
+  );
+END mms_unb2_fpga_sens;
+
+
+ARCHITECTURE str OF mms_unb2_fpga_sens IS
+
+  CONSTANT c_sens_nof_result : NATURAL := 1;  -- 
+  CONSTANT c_temp_high_w     : NATURAL := 7;  -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
+
+  SIGNAL sens_err  : STD_LOGIC;
+  SIGNAL sens_data : t_slv_8_arr(0 TO c_sens_nof_result-1);
+
+  SIGNAL temp_high : STD_LOGIC_VECTOR(c_temp_high_w-1 DOWNTO 0);
+
+BEGIN
+
+  u_unb2_fpga_sens_reg : ENTITY work.unb2_fpga_sens_reg
+  GENERIC MAP (
+    g_sim             => g_sim,
+    g_technology      => g_technology,
+    g_sens_nof_result => c_sens_nof_result,
+    g_temp_high       => g_temp_high  
+  )
+  PORT MAP (
+    -- Clocks and reset
+    mm_rst       => mm_rst,
+    mm_clk       => mm_clk,
+    start        => mm_start,
+    
+    -- Memory Mapped Slave in mm_clk domain
+    sla_in       => reg_mosi,
+    sla_out      => reg_miso,
+    
+    -- MM registers
+    --sens_err     => sens_err,  -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+    --sens_data    => sens_data,
+
+    -- Max temp threshold
+    temp_high    => temp_high
+  );
+  
+--  u_unb2_board_sens : ENTITY work.unb2_board_sens
+--  GENERIC MAP (
+--    g_sim             => g_sim,
+--    g_clk_freq        => g_clk_freq,
+--    g_temp_high       => g_temp_high,
+--    g_sens_nof_result => c_sens_nof_result
+--  )
+--  PORT MAP (
+--    clk          => mm_clk,
+--    rst          => mm_rst,
+--    start        => mm_start,
+--    -- i2c bus
+--    scl          => scl,
+--    sda          => sda,
+--    -- read results
+--    sens_evt     => OPEN,
+--    sens_err     => sens_err,
+--    sens_data    => sens_data
+--  );
+
+  -- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones) 
+  -- would produce -1 degrees so does not trigger a temperature alarm.
+  -- temp_high is 7 bits, preceded by a '0' to allow only positive temps to be set. 
+  temp_alarm <= '0';--<= '1' WHEN (SIGNED(sens_data(0)) > SIGNED('0' & temp_high)) ELSE '0';
+    
+END str;
+

boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd

@@ -156,9 +156,12 @@ PACKAGE unb2_board_peripherals_pkg IS
 
     -- dp_offload
     reg_dp_offload_tx_adr_w    : NATURAL;  -- = 1
+
+    -- pi_unb_fpga_sens
+    reg_fpga_sens_adr_w        : NATURAL;  -- = 1
   END RECORD;
   
-  CONSTANT c_unb2_board_peripherals_mm_reg_default    : t_c_unb2_board_peripherals_mm_reg := (TRUE, 10, 4, 10, 5, 10, 1, 1, 3, 1, 1, 1, 1, 1, 3, 3, 3, 16, 4, 6, 2, 2, 1, 4, 3, 6, 13, 12, 2, 32, 8, 2, 8, 10, 16, 1024, 14, 5, 3, 11, 2, 3, 5, 16, 11, 3, 1);
+  CONSTANT c_unb2_board_peripherals_mm_reg_default    : t_c_unb2_board_peripherals_mm_reg := (TRUE, 10, 4, 10, 5, 10, 1, 1, 3, 1, 1, 1, 1, 1, 3, 3, 3, 16, 4, 6, 2, 2, 1, 4, 3, 6, 13, 12, 2, 32, 8, 2, 8, 10, 16, 1024, 14, 5, 3, 11, 2, 3, 5, 16, 11, 3, 1, 1);
   
 END unb2_board_peripherals_pkg;
 

boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd

@@ -58,7 +58,9 @@ ARCHITECTURE rtl OF unb2_board_sens_ctrl IS
   CONSTANT ETH_MAX1617_ADR      : NATURAL := MAX1617_ADR_MID_LOW;      -- ETH  temperature sensor, slave address is "0101001"
   CONSTANT HOTSWAP_LTC4260_ADR  : NATURAL := LTC4260_ADR_LOW_LOW_LOW;  -- Hot swap controller,     slave address is "1000100";
 
-  CONSTANT LOC_POWER_TR_R : NATURAL := 16#0E#;
+  CONSTANT LOC_POWER_TR_R : NATURAL := 16#1C#; -- 0x0E
+  CONSTANT LOC_POWER_TR_R1 : NATURAL := 16#1D#; -- 0x0E
+  CONSTANT LOC_POWER_TR_R2 : NATURAL := 16#0F#; -- 0x0E
   CONSTANT LP_VOUT_MODE   : NATURAL := 16#20#;
   CONSTANT LP_VOUT        : NATURAL := 16#8B#;
   CONSTANT LP_IOUT        : NATURAL := 16#8C#;
@@ -72,10 +74,10 @@ ARCHITECTURE rtl OF unb2_board_sens_ctrl IS
   CONSTANT c_timeout_sda : NATURAL := sel_a_b(g_sim, 0, 16);  -- wait 16 * 256 = 4096 clk periods
   
   CONSTANT c_SEQ : t_SEQUENCE := (
-    SMBUS_READ_BYTE ,    LOC_POWER_TR_R, LP_VOUT_MODE,
-    SMBUS_READ_WORD ,    LOC_POWER_TR_R, LP_VOUT,
-    SMBUS_READ_WORD ,    LOC_POWER_TR_R, LP_IOUT,
-    SMBUS_READ_WORD ,    LOC_POWER_TR_R, LP_TEMP,
+    SMBUS_READ_BYTE ,    LOC_POWER_TR_R, LP_TEMP,--LP_VOUT_MODE,
+    SMBUS_C_NOP,--SMBUS_READ_BYTE ,    LOC_POWER_TR_R1, LP_TEMP,--LP_VOUT, -- SMBUS_READ_WORD
+    SMBUS_C_NOP,--SMBUS_READ_BYTE ,    LOC_POWER_TR_R2, LP_TEMP,--LP_IOUT, -- SMBUS_READ_WORD
+    SMBUS_C_NOP,--SMBUS_READ_BYTE ,    LOC_POWER_TR_R1, LP_VOUT_MODE, -- SMBUS_READ_WORD
 
     --SMBUS_READ_BYTE ,    FPGA_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
     --SMBUS_READ_BYTE ,     ETH_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,

boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012-2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Provide MM slave register for unb2_fpga_sens
+--
+
+LIBRARY IEEE, common_lib, fpga_temp_sens_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+
+
+ENTITY unb2_fpga_sens_reg IS
+  GENERIC (
+    g_sim             : BOOLEAN;
+    g_technology      : NATURAL;
+    g_sens_nof_result : NATURAL := 1;
+    g_temp_high       : NATURAL := 85
+  );
+  PORT (
+    -- Clocks and reset
+    mm_rst     : IN  STD_LOGIC;   -- reset synchronous with mm_clk
+    mm_clk     : IN  STD_LOGIC;   -- memory-mapped bus clock
+    start      : IN  STD_LOGIC;
+    
+    -- Memory Mapped Slave in mm_clk domain
+    sla_in     : IN  t_mem_mosi;  -- actual ranges defined by c_mm_reg
+    sla_out    : OUT t_mem_miso;  -- actual ranges defined by c_mm_reg
+    
+    -- MM registers
+    --sens_err   : IN  STD_LOGIC := '0';
+    --sens_data  : IN  t_slv_8_arr(0 TO g_sens_nof_result-1); -- FIXME should be OUT
+
+    -- Max temp output
+    temp_high  : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+  );
+END unb2_fpga_sens_reg;
+
+
+ARCHITECTURE str OF unb2_fpga_sens_reg IS
+
+  --SIGNAL i_temp_high    : STD_LOGIC_VECTOR(6 DOWNTO 0);
+                                  
+BEGIN
+
+  temp_high <= (others => '0'); --i_temp_high;
+
+  u_fpga_temp_sens: ENTITY fpga_temp_sens_lib.fpga_temp_sens
+  GENERIC MAP (
+    g_technology => g_technology,
+    g_sim        => g_sim
+  )
+  PORT MAP (
+    mm_clk      => mm_clk,
+    mm_rst      => mm_rst,
+
+    start_sense => start,
+
+    reg_mosi    => sla_in,
+    reg_miso    => sla_out
+  );
+
+END str;