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Commit e07a8aa0 authored by Eric Kooistra's avatar Eric Kooistra
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Put input delay buffer after WG.

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applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd
+ 62
− 65
View file @ e07a8aa0
......@@ -115,60 +115,17 @@ architecture str of sdp_adc_input_and_timing is
constant c_bs_block_size : natural := c_sdp_N_fft; -- =1024;
constant c_dp_fifo_dc_size : natural := 64;
-- Sosis and sosi arrays
signal dp_shiftram_snk_in_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
signal ant_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
-- Timestamp and streaming data arrays
signal bs_sosi : t_dp_sosi := c_dp_sosi_rst;
signal wg_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
signal ant_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
signal mux_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
signal nxt_mux_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
signal inp_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
signal st_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
begin
out_sosi_arr <= st_sosi_arr;
gen_rx : if g_no_rx = false generate
-----------------------------------------------------------------------------
-- Time delay: dp_shiftram
-- . copied from unb1_bn_capture_input (apertif)
-- Array range reversal is not done because everything is DOWNTO
-- . the input valid is always '1', even when there is no data
-----------------------------------------------------------------------------
p_dp_shiftram_snk_in_arr : process(rx_sosi_arr)
begin
dp_shiftram_snk_in_arr <= rx_sosi_arr;
for I in 0 to c_sdp_S_pn - 1 loop
-- ADC data is stored in the upper 14 bits of the jesd rx_sosi.
dp_shiftram_snk_in_arr(I).data <= RESIZE_DP_SDATA(rx_sosi_arr(I).data(c_sdp_W_adc_jesd - 1 downto (c_sdp_W_adc_jesd - c_sdp_W_adc) ));
-- Force valid.
dp_shiftram_snk_in_arr(I).valid <= '1';
end loop;
end process;
u_dp_shiftram : entity dp_lib.dp_shiftram
generic map (
g_nof_streams => c_sdp_S_pn,
g_nof_words => c_sdp_V_sample_delay,
g_data_w => c_sdp_W_adc,
g_use_sync_in => true
)
port map (
dp_rst => rx_rst,
dp_clk => rx_clk,
mm_rst => mm_rst,
mm_clk => mm_clk,
sync_in => bs_sosi.sync,
reg_mosi => reg_dp_shiftram_mosi,
reg_miso => reg_dp_shiftram_miso,
snk_in_arr => dp_shiftram_snk_in_arr,
src_out_arr => ant_sosi_arr
);
end generate;
-----------------------------------------------------------------------------
-- Timestamp
-----------------------------------------------------------------------------
......@@ -223,9 +180,8 @@ begin
);
-----------------------------------------------------------------------------
-- WG (Test Signal Generator)
-- WG (Waveworm Generator)
-----------------------------------------------------------------------------
u_wg_arr : entity diag_lib.mms_diag_wg_wideband_arr
generic map (
g_nof_streams => c_sdp_S_pn,
......@@ -262,44 +218,86 @@ begin
);
-----------------------------------------------------------------------------
-- ADC/WG Mux (Input Select)
-- ADC data
-----------------------------------------------------------------------------
p_rx_rewire_data : process(rx_sosi_arr)
begin
ant_sosi_arr <= rx_sosi_arr;
for I in 0 to c_sdp_S_pn - 1 loop
-- ADC data is stored in the upper 14 bits of the jesd rx_sosi.
ant_sosi_arr(I).data <= RESIZE_DP_SDATA(rx_sosi_arr(I).data(c_sdp_W_adc_jesd - 1 downto (c_sdp_W_adc_jesd - c_sdp_W_adc) ));
ant_sosi_arr(I).valid <= rx_sosi_arr(I).valid; -- connect, but not used
end loop;
end process;
-----------------------------------------------------------------------------
-- ADC/WG Mux (Input Select)
-----------------------------------------------------------------------------
gen_mux : for I in 0 to c_sdp_S_pn - 1 generate
p_sosi : process(ant_sosi_arr(I), wg_sosi_arr(I))
p_mux : process(ant_sosi_arr(I), wg_sosi_arr(I))
begin
-- Default use the ADC data
nxt_mux_sosi_arr(I).data <= ant_sosi_arr(I).data;
nxt_mux_sosi_arr(I).data <= ant_sosi_arr(I).data;
if wg_sosi_arr(I).valid = '1' then
-- Valid WG data overrules ADC data
nxt_mux_sosi_arr(I).data <= wg_sosi_arr(I).data;
end if;
-- Force valid = '1' to maintain synchronous processing, independent of
-- whether the ADC/WG data values are valid
nxt_mux_sosi_arr(I).valid <= '1';
end process;
end generate;
mux_sosi_arr <= nxt_mux_sosi_arr when rising_edge(rx_clk);
mux_sosi_arr <= nxt_mux_sosi_arr when rising_edge(rx_clk);
-----------------------------------------------------------------------------
-- Concatenate muxed data streams with bsn framing
-- Time delay: dp_shiftram
-- . copied from unb1_bn_capture_input (apertif)
-- Array range reversal is not done because everything is DOWNTO
-- . the input valid is always '1', even when there is no data, to avoid
-- shift misalignment between different signal inputs on different nodes
-- . the sync_in ensures that a new shift setting takes effect at the
-- bs_sosi.sync
-----------------------------------------------------------------------------
u_dp_shiftram : entity dp_lib.dp_shiftram
generic map (
g_nof_streams => c_sdp_S_pn,
g_nof_words => c_sdp_V_sample_delay,
g_data_w => c_sdp_W_adc,
g_use_sync_in => true
)
port map (
dp_rst => rx_rst,
dp_clk => rx_clk,
mm_rst => mm_rst,
mm_clk => mm_clk,
sync_in => bs_sosi.sync,
reg_mosi => reg_dp_shiftram_mosi,
reg_miso => reg_dp_shiftram_miso,
snk_in_arr => mux_sosi_arr,
src_out_arr => inp_sosi_arr
);
-----------------------------------------------------------------------------
-- Concatenate input data streams with BSN framing
-----------------------------------------------------------------------------
gen_concat : for I in 0 to c_sdp_S_pn - 1 generate
p_sosi : process(mux_sosi_arr(I), bs_sosi)
p_concat : process(mux_sosi_arr(I), bs_sosi)
begin
st_sosi_arr(I) <= bs_sosi;
st_sosi_arr(I).data <= mux_sosi_arr(I).data;
st_sosi_arr(I) <= bs_sosi; -- timestamp
st_sosi_arr(I).data <= inp_sosi_arr(I).data;
end process;
end generate;
---------------------------------------------------------------------------------------
-- Diagnostics on the bsn-framed data
-- . BSN Monitor (ToDo: can be removed as not part of the spec)
-- . Aduh monitor
-- . Data Buffer (variable depth from 1k-128k)
-- Diagnostics on the BSN-framed data
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- BSN monitor (Block Checker)
-- BSN monitor, for sync, BSN and nof samples per sync
---------------------------------------------------------------------------------------
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
generic map (
......@@ -322,7 +320,7 @@ begin
);
-----------------------------------------------------------------------------
-- Monitor ADU/WG output
-- Monitor ADU/WG output, for mean sum and power sum
-----------------------------------------------------------------------------
u_aduh_monitor : entity aduh_lib.mms_aduh_monitor_arr
generic map (
......@@ -337,7 +335,7 @@ begin
mm_rst => mm_rst,
mm_clk => mm_clk,
reg_mosi => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
reg_mosi => reg_aduh_monitor_mosi,
reg_miso => reg_aduh_monitor_miso,
buf_mosi => c_mem_mosi_rst, -- Unused
buf_miso => OPEN,
......@@ -350,9 +348,8 @@ begin
);
-----------------------------------------------------------------------------
-- Diagnostic Data Buffer
-- Diagnostic Data Buffer, for capturing raw time series data
-----------------------------------------------------------------------------
u_diag_data_buffer_bsn : entity diag_lib.mms_diag_data_buffer
generic map (
g_nof_streams => c_sdp_S_pn,
......
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