Try c_nof_blocks=64 and c_ena_pre_transp=False, must match settings in unb1_ddr3_reorder.vhd.

boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd

@@ -86,13 +86,13 @@ ARCHITECTURE str OF unb1_ddr3_reorder IS
   CONSTANT c_aux              : t_c_unb1_board_aux := c_unb1_board_aux;
   CONSTANT c_app_led_en       : BOOLEAN := TRUE;
 
-  CONSTANT c_ena_pre_transp   : BOOLEAN := TRUE;
+  CONSTANT c_ena_pre_transp   : BOOLEAN := FALSE;
   CONSTANT c_wr_chunksize     : NATURAL := 176;
   CONSTANT c_rd_chunksize     : NATURAL := 16;
   CONSTANT c_rd_nof_chunks    : NATURAL := 11;
   CONSTANT c_rd_interval      : NATURAL := c_rd_chunksize;
   CONSTANT c_gapsize          : NATURAL := 0;
-  CONSTANT c_nof_blocks       : NATURAL := sel_a_b(g_sim, 16, 800000);
+  CONSTANT c_nof_blocks       : NATURAL := 64; --sel_a_b(g_sim, 16, 800000);
   CONSTANT c_nof_streams      : NATURAL := 1;
   CONSTANT c_in_dat_w         : NATURAL := 64;
   CONSTANT c_reorder_seq_conf : t_reorder_seq := (c_wr_chunksize,