Skip to content
Snippets Groups Projects
Commit dff65110 authored by Job van Wee's avatar Job van Wee
Browse files

solved using rising_edge(not clock)

parent de25b74a
No related branches found
No related tags found
1 merge request!215Resolve L2SDP-660
Pipeline #26140 passed
Stage: simulation
Stage: synthesis
Hide whitespace changes
Inline Side-by-side
applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+ 2
− 1
View file @ dff65110
......@@ -67,7 +67,7 @@ ARCHITECTURE str OF ddrctrl IS
-- signals for connecting the components
SIGNAL data : STD_LOGIC_VECTOR(c_out_data_w-1 DOWNTO 0);
SIGNAL sosi : t_dp_sosi;
SIGNAL sosi : t_dp_sosi := c_dp_sosi_init;
BEGIN
......@@ -106,6 +106,7 @@ BEGIN
g_sim_model => g_sim_model -- determens if this is a simulation
)
PORT MAP(
clk => clk,
rst => rst,
in_sosi => sosi, -- input data
out_mosi => out_mosi -- output data
......
applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd
+ 13
− 12
View file @ dff65110
......@@ -45,6 +45,7 @@ ENTITY ddrctrl_address_counter IS
g_sim_model : BOOLEAN := TRUE -- determens if this is a simulation
);
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
in_sosi : IN t_dp_sosi; -- input data
out_mosi : OUT t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst -- output data
......@@ -57,30 +58,30 @@ ARCHITECTURE rtl OF ddrctrl_address_counter IS
-- constants for readability
CONSTANT c_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- the with of the input data and output data, 576
CONSTANT c_adr_w : NATURAL := sel_a_b(g_sim_model, 4, func_tech_ddr_ctlr_address_w( g_tech_ddr )); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
CONSTANT c_max_adr : NATURAL := 2**(c_adr_w) - 1; -- the maximal address that is possible within the vector length of the address
CONSTANT c_max_adr : NATURAL := 2**(c_adr_w)-1; -- the maximal address that is possible within the vector length of the address
-- signal for storing address
SIGNAL s_adr : NATURAL range 0 to 2**(c_adr_w)-1 := 0; -- a signal that contains the address
BEGIN
-- The data is directly put through.
out_mosi.wrdata(c_data_w - 1 DOWNTO 0) <= in_sosi.data(c_data_w - 1 DOWNTO 0);
out_mosi.wr <= in_sosi.valid;
out_mosi.address(c_adr_w -1 DOWNTO 0) <= TO_UVEC(s_adr, c_adr_w);
-- Increments the address each time in_sosi.valid = '1', if address = c_max_adr the address is reset to 0.
p_adr : PROCESS(rst, in_sosi.valid)
p_adr : PROCESS(rst, clk)
BEGIN
IF rst = '1' THEN
s_adr <= 0;
ELSIF rising_edge(in_sosi.valid) THEN
IF s_adr = c_max_adr THEN
IF rising_edge(clk) THEN
out_mosi.wrdata(c_data_w - 1 DOWNTO 0) <= in_sosi.data(c_data_w - 1 DOWNTO 0);
out_mosi.wr <= in_sosi.valid;
IF rst = '1' THEN
s_adr <= 0;
ELSE
s_adr <= s_adr + 1;
ELSIF in_sosi.valid = '1' THEN
IF s_adr = c_max_adr THEN
s_adr <= 0;
ELSE
s_adr <= s_adr + 1;
END IF;
END IF;
END IF;
END PROCESS;
END rtl;
applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+ 24
− 11
View file @ dff65110
......@@ -86,6 +86,8 @@ ARCHITECTURE tb OF tb_ddrctrl IS
SIGNAL in_data_cnt : NATURAL := 0; -- signal which contains the amount of times there has been input data for ddrctrl_repack.vhd
SIGNAL test_running : STD_LOGIC := '0'; -- signal to tell wheter the testing has started
SIGNAL lag_due_reset : NATURAL := 0; -- signal to hold the address lag after a rest
SIGNAL d_lag_due_reset : NATURAL := 0;
SIGNAL d_rst : STD_LOGIC := '0';
BEGIN
......@@ -109,42 +111,53 @@ BEGIN
in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= c_total_vector(g_data_w*(I+1)+J*c_in_data_w-1 DOWNTO g_data_w*I+J*c_in_data_w);
END LOOP;
WAIT FOR c_clk_period*1;
in_data_cnt <= in_data_cnt + 1;
in_data_cnt <= in_data_cnt+1;
END LOOP;
test_running <= '0';
-- stopping the testbench
WAIT FOR c_clk_period*5;
tb_end <= '1';
ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
END PROCESS;
-- excecuting the reset test
p_test_reset : PROCESS
BEGIN
rst <= '0';
WAIT FOR c_clk_period*(c_adr_size+3);
--WAIT FOR c_clk_period*1;
IF lag_due_reset + TO_UINT(out_mosi.address) >= c_adr_size THEN
lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address)-c_adr_size;
ELSE
lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address);
END IF;
WAIT FOR c_clk_period*(c_adr_size+3);
rst <= '1';
WAIT FOR c_clk_period*1;
END PROCESS;
-- generating compare data for out_mosi
p_out_mosi : PROCESS
BEGIN
WAIT UNTIL rising_edge(clk);
if rising_edge(clk) THEN
d_lag_due_reset <= lag_due_reset;
d_rst <= rst;
END IF;
END PROCESS;
-- verifying if the address is correct by keeping trach of the address
p_verify_address : PROCESS
BEGIN
FOR I IN 0 TO c_adr_size-1 LOOP
WAIT UNTIL out_mosi.wr = '1';
IF rst = '1' THEN
IF d_rst = '1' THEN
WAIT UNTIL out_mosi.wr = '1';
END IF;
IF I >= lag_due_reset THEN
ASSERT I-lag_due_reset = TO_UINT(out_mosi.address) REPORT "Wrong address, 1, I = " & NATURAL'image(I-lag_due_reset) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
IF I >= d_lag_due_reset THEN
ASSERT I-d_lag_due_reset = TO_UINT(out_mosi.address) REPORT "Wrong address, 1, I = " & NATURAL'image(I-d_lag_due_reset) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
ELSE
ASSERT (I-lag_due_reset)+c_adr_size = TO_UINT(out_mosi.address) REPORT "Wrong address, 2, I = " & NATURAL'image((I-lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
ASSERT (I-d_lag_due_reset)+c_adr_size = TO_UINT(out_mosi.address) REPORT "Wrong address, 2, I = " & NATURAL'image((I-d_lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
END IF;
END LOOP;
END PROCESS;
......@@ -159,17 +172,17 @@ BEGIN
WAIT UNTIL out_mosi.wr = '1' AND test_running = '1';
IF out_data_cnt >= 1 THEN
IF out_data_cnt mod 2 = 0 THEN
ctr_of := c_in_data_w*in_data_cnt-c_out_data_w*out_data_cnt;
ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) & ", out_of = " & NATURAL'image(out_of) SEVERITY ERROR;
ctr_of := c_in_data_w*(in_data_cnt-1)-c_out_data_w*out_data_cnt;
ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) & ", out_of = " & NATURAL'image(out_of) SEVERITY ERROR;
END IF;
ASSERT out_mosi.wrdata(c_out_data_w-1 DOWNTO 0) = c_total_vector(c_out_data_w*out_data_cnt-1 DOWNTO c_out_data_w*(out_data_cnt-1)) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR;
ASSERT out_mosi.wrdata(c_out_data_w-1 DOWNTO 0) = c_total_vector(c_out_data_w*out_data_cnt-1 DOWNTO c_out_data_w*(out_data_cnt-1)) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR;
END IF;
out_data_cnt := out_data_cnt+1;
END PROCESS;
-- DUT
u_ddrctrl_pack : ENTITY work.ddrctrl
u_ddrctrl : ENTITY work.ddrctrl
GENERIC MAP (
g_tech_ddr => g_tech_ddr,
g_sim_model => g_sim_model,
......
applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd
+ 29
− 10
View file @ dff65110
......@@ -62,9 +62,13 @@ ARCHITECTURE tb OF tb_ddrctrl_address_counter IS
-- testbench signals
SIGNAL tb_end : STD_LOGIC := '0'; -- signal to turn the testbench off
SIGNAL in_data : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0); -- signal which contains the data that is set as input
SIGNAL in_data_enable : STD_LOGIC; -- signal to determen if in_data is ready for reading
SIGNAL in_data : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0) := (OTHERS => '0'); -- signal which contains the data that is set as input
SIGNAL d_in_data : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL in_data_enable : STD_LOGIC := '0'; -- signal to determen if in_data is ready for reading
SIGNAL d_in_data_enable : STD_LOGIC := '0';
SIGNAL lag_due_reset : NATURAL := 0; -- signal to hold the address lag after a rest
SIGNAL d_lag_due_reset : NATURAL := 0;
SIGNAL d_rst : STD_LOGIC := '0';
BEGIN
......@@ -97,16 +101,29 @@ BEGIN
-- stopping the test
WAIT FOR c_clk_period*4;
tb_end <= '1';
ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
END PROCESS;
-- generating compare data for out_mosi
p_out_mosi : PROCESS
BEGIN
WAIT UNTIL rising_edge(clk);
if rising_edge(clk) THEN
d_in_data_enable <= in_data_enable;
d_in_data <= in_data;
d_lag_due_reset <= lag_due_reset;
d_rst <= rst;
END IF;
END PROCESS;
-- verifying if the data is correct and if valid is correct
p_verify_data_valid : PROCESS
BEGIN
WAIT UNTIL rising_edge(clk);
IF rising_edge(clk) THEN
ASSERT in_sosi.data(c_data_w-1 DOWNTO 0) = out_mosi.wrdata(c_data_w-1 DOWNTO 0) REPORT "in_sosi.data does not match out_mosi.wrdata" SEVERITY ERROR;
ASSERT in_sosi.valid = out_mosi.wr REPORT "in_sosi.valid does not match out_mosi.wr" SEVERITY ERROR;
ASSERT d_in_data(c_data_w-1 DOWNTO 0) = out_mosi.wrdata(c_data_w-1 DOWNTO 0) REPORT "in_sosi.data does not match out_mosi.wrdata" SEVERITY ERROR;
ASSERT d_in_data_enable = out_mosi.wr REPORT "in_sosi.valid does not match out_mosi.wr" SEVERITY ERROR;
END IF;
END PROCESS;
......@@ -114,12 +131,13 @@ BEGIN
p_test_reset : PROCESS
BEGIN
rst <= '0';
WAIT FOR c_clk_period*(c_adr_size+3);
--WAIT FOR c_clk_period*1;
IF lag_due_reset + TO_UINT(out_mosi.address) >= c_adr_size THEN
lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address)-c_adr_size;
ELSE
lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address);
END IF;
WAIT FOR c_clk_period*(c_adr_size+3);
rst <= '1';
WAIT FOR c_clk_period*1;
END PROCESS;
......@@ -129,13 +147,13 @@ BEGIN
BEGIN
FOR I IN 0 TO c_adr_size-1 LOOP
WAIT UNTIL out_mosi.wr = '1';
IF rst = '1' THEN
IF d_rst = '1' THEN
WAIT UNTIL out_mosi.wr = '1';
END IF;
IF I >= lag_due_reset THEN
ASSERT I-lag_due_reset = TO_UINT(out_mosi.address) REPORT "Wrong address, 1, I = " & NATURAL'image(I-lag_due_reset) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
IF I >= d_lag_due_reset THEN
ASSERT I-d_lag_due_reset = TO_UINT(out_mosi.address) REPORT "Wrong address, 1, I = " & NATURAL'image(I-d_lag_due_reset) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
ELSE
ASSERT (I-lag_due_reset)+c_adr_size = TO_UINT(out_mosi.address) REPORT "Wrong address, 2, I = " & NATURAL'image((I-lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
ASSERT (I-d_lag_due_reset)+c_adr_size = TO_UINT(out_mosi.address) REPORT "Wrong address, 2, I = " & NATURAL'image((I-d_lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
END IF;
END LOOP;
END PROCESS;
......@@ -148,6 +166,7 @@ BEGIN
g_sim_model => g_sim_model
)
PORT MAP (
clk => clk,
rst => rst,
in_sosi => in_sosi,
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment