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Commit dfcf97ce authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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simulation for 1GbE channel testing now

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boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+ 19
− 19
View file @ dfcf97ce
...@@ -49,7 +49,7 @@ ENTITY unb2_test IS ...@@ -49,7 +49,7 @@ ENTITY unb2_test IS
); );
PORT ( PORT (
-- GENERAL -- GENERAL
--CLK : IN STD_LOGIC; -- System Clock - not used as PLL generates dp_clk. CLK : IN STD_LOGIC; -- System Clock
PPS : IN STD_LOGIC; -- System Sync PPS : IN STD_LOGIC; -- System Sync
WDI : OUT STD_LOGIC; -- Watchdog Clear WDI : OUT STD_LOGIC; -- Watchdog Clear
INTA : INOUT STD_LOGIC; -- FPGA interconnect line INTA : INOUT STD_LOGIC; -- FPGA interconnect line
...@@ -131,8 +131,8 @@ ARCHITECTURE str OF unb2_test IS ...@@ -131,8 +131,8 @@ ARCHITECTURE str OF unb2_test IS
-- Block generator -- Block generator
CONSTANT c_bg_block_size : NATURAL := 900; CONSTANT c_bg_block_size : NATURAL := 900; -- FIXME: select on g_sim
CONSTANT c_bg_gapsize : NATURAL := 100; CONSTANT c_bg_gapsize : NATURAL := 100; -- FIXME: select on g_sim
CONSTANT c_bg_blocks_per_sync : NATURAL := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second CONSTANT c_bg_blocks_per_sync : NATURAL := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
CONSTANT c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default) CONSTANT c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
'0', -- enable_sync '0', -- enable_sync
...@@ -264,10 +264,10 @@ ARCHITECTURE str OF unb2_test IS ...@@ -264,10 +264,10 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL reg_remu_miso : t_mem_miso; SIGNAL reg_remu_miso : t_mem_miso;
-- 10GbE -- 10GbE
SIGNAL serial_10G_tx_arr : STD_LOGIC_VECTOR(c_nof_streams-1 downto 0) := (OTHERS=>'0'); SIGNAL serial_10G_tx_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_hw_nof_lines-1 downto 0) := (OTHERS=>'0');
SIGNAL serial_10G_rx_arr : STD_LOGIC_VECTOR(c_nof_streams-1 downto 0); SIGNAL serial_10G_rx_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_hw_nof_lines-1 downto 0);
SIGNAL serial_10G_tx_dummy : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 0); SIGNAL i_serial_10G_tx_arr : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0);
SIGNAL serial_10G_rx_dummy : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 0); SIGNAL i_serial_10G_rx_arr : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0);
SIGNAL reg_tr_10GbE_mosi : t_mem_mosi; SIGNAL reg_tr_10GbE_mosi : t_mem_mosi;
SIGNAL reg_tr_10GbE_miso : t_mem_miso; SIGNAL reg_tr_10GbE_miso : t_mem_miso;
...@@ -344,7 +344,7 @@ BEGIN ...@@ -344,7 +344,7 @@ BEGIN
g_aux => c_unb2_board_aux, g_aux => c_unb2_board_aux,
g_udp_offload => c_use_1GbE, g_udp_offload => c_use_1GbE,
g_udp_offload_nof_streams => c_nof_streams, g_udp_offload_nof_streams => c_nof_streams,
g_dp_clk_use_pll => FALSE g_dp_clk_use_pll => TRUE
) )
PORT MAP ( PORT MAP (
-- Clock an reset signals -- Clock an reset signals
...@@ -357,7 +357,7 @@ BEGIN ...@@ -357,7 +357,7 @@ BEGIN
mm_rst => mm_rst, mm_rst => mm_rst,
dp_rst => dp_rst, dp_rst => dp_rst,
dp_clk => OPEN, dp_clk => dp_clk,
dp_pps => OPEN, dp_pps => OPEN,
dp_rst_in => dp_rst, dp_rst_in => dp_rst,
...@@ -422,7 +422,7 @@ BEGIN ...@@ -422,7 +422,7 @@ BEGIN
-- FPGA pins -- FPGA pins
-- . General -- . General
CLK => '0', -- PLL generated 200MHz dp_clk is used. CLK => CLK,
PPS => PPS, PPS => PPS,
WDI => WDI, WDI => WDI,
INTA => INTA, INTA => INTA,
...@@ -784,23 +784,23 @@ BEGIN ...@@ -784,23 +784,23 @@ BEGIN
snk_in_arr => dp_offload_tx_src_out_arr, snk_in_arr => dp_offload_tx_src_out_arr,
-- Serial IO -- Serial IO
serial_tx_arr => serial_10G_tx_arr, serial_tx_arr => i_serial_10G_tx_arr,
serial_rx_arr => serial_10G_rx_arr serial_rx_arr => i_serial_10G_rx_arr
); );
gen_wires: FOR i IN 0 TO c_nof_streams-1 GENERATE
serial_10G_tx_arr(i) <= i_serial_10G_tx_arr(i);
i_serial_10G_rx_arr(i) <= serial_10G_rx_arr(i);
END GENERATE;
serial_10G_tx_dummy(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 1) <= (OTHERS=>'0'); serial_10G_tx_arr(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO c_nof_streams) <= (OTHERS=>'0');
serial_10G_tx_dummy(0 DOWNTO 0) <= serial_10G_tx_arr;
serial_10G_rx_dummy(0 DOWNTO 0) <= serial_10G_rx_arr;
u_front_io : ENTITY unb2_board_lib.unb2_board_front_io u_front_io : ENTITY unb2_board_lib.unb2_board_front_io
PORT MAP ( PORT MAP (
serial_tx_arr => serial_10G_tx_dummy, serial_tx_arr => serial_10G_tx_arr,
serial_rx_arr => serial_10G_rx_dummy, serial_rx_arr => serial_10G_rx_arr,
-- Serial I/O -- Serial I/O
-- front transceivers -- front transceivers
......
boards/uniboard2/designs/unb2_test/tb/python/tc_unb2_test.py
+ 241
− 0
View file @ dfcf97ce
...@@ -35,6 +35,13 @@ Description: ...@@ -35,6 +35,13 @@ Description:
- write to wdi to force reload from bank 0 - write to wdi to force reload from bank 0
- flash access: write image to bank 1 - flash access: write image to bank 1
- remote update: start image in bank 1 - remote update: start image in bank 1
- read status MAC 10GbE
- read status PHY XAUI
- BG - DB tests for 1 port on 1 FPGA
- BG - DB tests for all ports on all FPGAs
- link test between ports on the same FPGA (same XO)
- link test between ports on different Uniboards (XO drift)
- stable link after image restart
""" """
...@@ -42,6 +49,7 @@ Description: ...@@ -42,6 +49,7 @@ Description:
# System imports # System imports
import sys import sys
import signal import signal
import random
import test_case import test_case
import node_io import node_io
import pi_system_info import pi_system_info
...@@ -51,6 +59,9 @@ import pi_wdi ...@@ -51,6 +59,9 @@ import pi_wdi
import pi_epcs import pi_epcs
import pi_remu import pi_remu
import pi_eth import pi_eth
import pi_bsn_monitor
import pi_diag_block_gen
import pi_diag_data_buffer
import pi_debug_wave import pi_debug_wave
from tools import * from tools import *
...@@ -58,6 +69,228 @@ from common import * ...@@ -58,6 +69,228 @@ from common import *
from pi_common import * from pi_common import *
def show_compare_arrays(tc,a,b):
import numpy as np
tc.append_log(5, 'Compare array A:\n%s' % np.asarray(a))
tc.append_log(5, 'With array B:\n%s' % np.asarray(b))
compared = (np.asarray(a) == np.asarray(b))
tc.append_log(5, 'Result:\n%s' % compared)
return (not False in compared)
def test_BG_to_DB(tc,io,cmd):
if tc.number == 1:
use_pps=True
tc.set_section_id('Test BG-DB (pps sync) - ')
else:
use_pps=False
tc.set_section_id('Test BG-DB - ')
tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>')
if use_pps==True: ppsh = pi_ppsh.PiPpsh(tc, io)
tc.set_section_id('Read - ')
nof_streams=3
blocksize=0
Bg = pi_diag_block_gen.PiDiagBlockGen(tc,io,nofChannels=nof_streams,ramSizePerChannel=blocksize)
Bg.write_disable()
settings = Bg.read_block_gen_settings()
samples_per_packet = settings[0][1]
gapsize = settings[0][3]
blocksize = pow(2, ceil_log2(samples_per_packet+gapsize))
Bg = pi_diag_block_gen.PiDiagBlockGen(tc,io,nofChannels=nof_streams, ramSizePerChannel=blocksize)
#Bg.write_block_gen_settings(samplesPerPacket=700, blocksPerSync=781250, gapSize=300, memLowAddr=0, memHighAddr=701, BSNInit=42)
Db = pi_diag_data_buffer.PiDiagDataBuffer(tc,io,nofStreams=nof_streams,ramSizePerStream=blocksize)
resetptrn = [0xc1ea1ed1]*blocksize #samples_per_packet + [0]*(blocksize-samples_per_packet)
for s in tc.gpNumbers:
Db.overwrite_data_buffer(resetptrn,streamNr=s,vLevel=9)
# Trigger by reading databuffers:
for s in tc.gpNumbers:
Db.read_data_buffer(streamNr=s,vLevel=9)
if use_pps==True:
Bg.write_enable_pps()
ppsh.wait_until_pps(vLevel=6)
else:
Bg.write_enable()
bg_ram = []
for s in tc.gpNumbers:
ram = Bg.read_waveform_ram(channelNr=s,vLevel=5)
rram=[]
for r in ram:
ram_10G = list(r) # () -> []
# truncate: in 10GbE the data is only sized 700
ram_10G = ram_10G[:-(blocksize-700)] # [:-(blocksize-samples_per_packet)]
rram.append(ram_10G)
bg_ram.append(rram)
db_ram = []
for s in tc.gpNumbers:
databuf = Db.read_data_buffer(streamNr=s,vLevel=5)
rram=[]
for r in databuf:
ram_10G = r
# truncate: in 10GbE the data is only sized 700
ram_10G = ram_10G[:-(blocksize-700)] # [:-(blocksize-samples_per_packet)]
rram.append(ram_10G)
db_ram.append(rram)
#print 'bg_ram=',bg_ram
#print 'db_ram=',db_ram
tc.append_log(5, 'number of BG streams=%d number of DB streams=%d per stream:' % (len(bg_ram),len(db_ram)))
for st in range(len(bg_ram)):
tc.append_log(5, 'BG=%d blocks with' % len(bg_ram[st]))
for b in range(len(bg_ram[st])):
tc.append_log(5, '%d words' % len(bg_ram[st][b]))
tc.append_log(5, 'DB=%d blocks with' % len(db_ram[st]))
for b in range(len(db_ram[st])):
tc.append_log(5, '%d words' % len(db_ram[st][b]))
tc.set_section_id('Compare (BG==DB) - ')
compared = (bg_ram == db_ram)
tc.append_log(3, '')
tc.append_log(1, '>>> (BG==DB): %s' % compared)
tc.append_log(3, '')
if compared==False:
tc.set_result('FAILED')
show_compare_arrays(tc,bg_ram,db_ram)
Bg.write_disable()
def get_BG_blocksize(tc,io):
nof_streams=3
blocksize=0
Bg = pi_diag_block_gen.PiDiagBlockGen(tc,io,nofChannels=nof_streams,ramSizePerChannel=blocksize)
settings = Bg.read_block_gen_settings()
samples_per_packet = settings[0][1]
gapsize = settings[0][3]
blocksize = pow(2, ceil_log2(samples_per_packet+gapsize))
return blocksize
def write_BG(tc,io,buf):
tc.set_section_id('Write BG - ')
nof_streams=3
blocksize=get_BG_blocksize(tc,io)
Bg = pi_diag_block_gen.PiDiagBlockGen(tc,io,nofChannels=nof_streams, ramSizePerChannel=blocksize)
Bg.write_disable()
for s in tc.gpNumbers:
Bg.write_waveform_ram(buf,channelNr=s)
def write_BG_00100(tc,io,cmd):
tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>')
blocksize=get_BG_blocksize(tc,io)
ptrn = [0]*blocksize
ptrn[blocksize/2]=1
write_BG(tc,io,ptrn)
def write_BG_ff7ff(tc,io,cmd):
tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>')
blocksize=get_BG_blocksize(tc,io)
ptrn = [0xffffffff]*blocksize
ptrn[blocksize/2]=0xffff7fff
write_BG(tc,io,ptrn)
def write_BG_rand(tc,io,cmd):
tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>')
blocksize=get_BG_blocksize(tc,io)
random.seed(10)
ptrn = [random.randint(0,0xffffffff) for r in range(blocksize)]
write_BG(tc,io,ptrn)
def write_BG_count(tc,io,cmd):
tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>')
blocksize=get_BG_blocksize(tc,io)
ptrn = range(blocksize)
write_BG(tc,io,ptrn)
def test_tr_xaui(tc,io,cmd):
tc.set_section_id('Read tr xaui status - ')
tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>')
tc.append_log(3, '')
from pi_tr_xaui import REGMAP,PiTrXaui
on_execute(class_definition=PiTrXaui,regmap=REGMAP)
def verify_10GbE_status(tc,item_name,item_value):
no_errors = [0]*len(tc.nodeNrs)
err=[]
for s in range(len(item_value)): err.append(item_value[s][2][0])
tc.append_log(3,'%s=%s' % (item_name,err))
if err != no_errors:
tc.set_result('FAILED')
def test_tr_10GbE(tc,io,cmd):
tc.set_section_id('tr_10GbE status - ')
tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>')
nof_streams=3
from pi_tr_10GbE import REGMAP,PiTr10GbE,ADDR_W
tr10 = PiTr10GbE(tc,io,nof_inst=nof_streams)
if tc.verbosity > 5:
on_execute(class_definition=PiTr10GbE,regmap=REGMAP) # this reads/shows ALL status
for s in tc.gpNumbers:
inst_offs = s*2**ADDR_W
# set rx/tr _frame_maxlength to 9000 (jumbo) as it inits at 1518 and causing frame errors:
frame_size_jumbo = 9000
tr10.write_reg(tc.nodeNrs,'REG_TR_10GBE',inst_offs+(REGMAP['rx_frame_maxlength'][2][0]),[frame_size_jumbo])
tr10.write_reg(tc.nodeNrs,'REG_TR_10GBE',inst_offs+(REGMAP['tx_frame_maxlength'][2][0]),[frame_size_jumbo])
tc.set_section_id('Read/verify tr_10GbE status over Nodes %s stream=%d ' % (tc.nodeNrs,s))
tc.append_log(3, '')
status_names = ['rx_stats_framesErr','tx_stats_framesErr','rx_stats_framesCRCErr', \
'tx_stats_framesCRCErr','rx_stats_etherStatsCRCErr','tx_stats_etherStatsCRCErr']
for stat_name in status_names:
verify_10GbE_status(tc,stat_name,tr10.read_reg(tc.nodeNrs,'REG_TR_10GBE',inst_offs+(REGMAP[stat_name][2][0]),1))
def test_bsn_mon(tc,io,cmd):
tc.set_section_id('Read BSN monitor status - ')
tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>')
Bsn = pi_bsn_monitor.PiBsnMonitor(tc,io)
Bsn.read_bsn_monitor()
tc.append_log(3, '')
def test_info(tc,io,cmd): def test_info(tc,io,cmd):
tc.set_section_id('Read System Info - ') tc.set_section_id('Read System Info - ')
tc.append_log(3, '>>>') tc.append_log(3, '>>>')
...@@ -248,6 +481,14 @@ Cmd['PPSH'] = (test_ppsh, 'using pi_ppsh to read PPSH capture count (acces ...@@ -248,6 +481,14 @@ Cmd['PPSH'] = (test_ppsh, 'using pi_ppsh to read PPSH capture count (acces
Cmd['ETH'] = (test_eth, 'using pi_eth to read eth status','') Cmd['ETH'] = (test_eth, 'using pi_eth to read eth status','')
Cmd['REMU'] = (test_remu, 'using pi_remu to load user image (access REG_REMU)','') Cmd['REMU'] = (test_remu, 'using pi_remu to load user image (access REG_REMU)','')
Cmd['WDI'] = (test_wdi, 'using pi_wdi to reset to image in bank 0 (access REG_WDI)','') Cmd['WDI'] = (test_wdi, 'using pi_wdi to reset to image in bank 0 (access REG_WDI)','')
Cmd['XAUI'] = (test_tr_xaui, 'using pi_tr_xaui to read xaui status (access REG_TR_XAUI)','(-r for addressing streams)')
Cmd['10GBE'] = (test_tr_10GbE,'using pi_tr_10GbE to read 10GbE status (access REG_TR_10GBE)','(-r for addressing streams)')
Cmd['BSN'] = (test_bsn_mon, 'using pi_bsn_monitor to read BSN monitor (access REG_BSN_MONITOR)','')
Cmd['BGDB'] = (test_BG_to_DB,'using BG (pi_diag_block_gen.py) and DB (pi_diag_data_buffer.py)','(-r for addressing streams, -n1 for use pps)')
Cmd['BGs00100'] = (write_BG_00100,'set test BG pattern ...000000000010000000000...','(-r for addressing streams)')
Cmd['BGsff7ff'] = (write_BG_ff7ff,'set test BG pattern ...ffffffffff7ffffffffff...','(-r for addressing streams)')
Cmd['BGsrand'] = (write_BG_rand, 'set test BG pattern with pseudo random (seed=10)','(-r for addressing streams)')
Cmd['BGscount'] = (write_BG_count,'set test BG pattern with counter data','(-r for addressing streams)')
Cmd['sleep1'] = (sleep, 'Sleep 1 second','') Cmd['sleep1'] = (sleep, 'Sleep 1 second','')
Cmd['sleep5'] = (sleep, 'Sleep 5 seconds','') Cmd['sleep5'] = (sleep, 'Sleep 5 seconds','')
Cmd['example'] = (show_help, 'show several example commands','') Cmd['example'] = (show_help, 'show several example commands','')
......
boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
+ 5
− 3
View file @ dfcf97ce
...@@ -42,12 +42,14 @@ ...@@ -42,12 +42,14 @@
-- > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim -- > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
-- --
LIBRARY IEEE, common_lib, unb2_board_lib, i2c_lib; LIBRARY IEEE, common_lib, unb2_board_lib, i2c_lib, technology_lib, tech_pll_lib;
USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL; USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL; USE common_lib.common_pkg.ALL;
USE unb2_board_lib.unb2_board_pkg.ALL; USE unb2_board_lib.unb2_board_pkg.ALL;
USE common_lib.tb_common_pkg.ALL; USE common_lib.tb_common_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE tech_pll_lib.tech_pll_component_pkg.ALL;
ENTITY tb_unb2_test IS ENTITY tb_unb2_test IS
GENERIC ( GENERIC (
...@@ -71,7 +73,7 @@ ARCHITECTURE tb OF tb_unb2_test IS ...@@ -71,7 +73,7 @@ ARCHITECTURE tb OF tb_unb2_test IS
CONSTANT c_cable_delay : TIME := 12 ns; CONSTANT c_cable_delay : TIME := 12 ns;
CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
CONSTANT c_clk_period : TIME := 5 ns; CONSTANT c_clk_period : TIME := 5 ns;
CONSTANT c_sa_clk_period : TIME := 1.552 ns; -- 644 MHz CONSTANT c_sa_clk_period : TIME := tech_pll_clk_644_period; -- 644 MHz
CONSTANT c_pps_period : NATURAL := 1000; CONSTANT c_pps_period : NATURAL := 1000;
-- DUT -- DUT
...@@ -159,7 +161,7 @@ BEGIN ...@@ -159,7 +161,7 @@ BEGIN
) )
PORT MAP ( PORT MAP (
-- GENERAL -- GENERAL
--CLK => clk, CLK => clk,
PPS => pps, PPS => pps,
WDI => WDI, WDI => WDI,
INTA => INTA, INTA => INTA,
......
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