-Added the following line to the hdllib.cfg files:

 quartus_sdc_files =
    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc

applications/apertif/designs/apertif_unb1_correlator/hdllib.cfg

@@ -38,4 +38,5 @@ quartus_vhdl_files =
 quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/apertif_unb1_correlator/qsys_apertif_unb1_correlator/synthesis/qsys_apertif_unb1_correlator.qip
 
-    
+quartus_sdc_files =
\ No newline at end of file
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc    

applications/apertif/designs/apertif_unb1_fn_bf_emu/hdllib.cfg

@@ -34,4 +34,5 @@ quartus_qip_files =
 modelsim_search_libraries =                                                                                            
     altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
     altera     lpm     sgate     altera_mf     altera_lnsim     stratixiv     stratixiv_hssi     stratixiv_pcie_hip    
-
+quartus_sdc_files =
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc