Moved rtl and stratixiv ip for common_mult and common_complex_mult from UNB to RadioHDL

libraries/technology/mult/hdllib.cfg

+hdl_lib_name = tech_mult
+hdl_library_clause_name = tech_mult_lib
+hdl_lib_uses_synth = common
+                     technology
+                     ip_stratixiv_mult
+hdl_lib_uses_sim = 
+
+hdl_lib_technology = 
+
+synth_files =
+    tech_mult_component_pkg.vhd
+    tech_complex_mult.vhd
+    tech_mult.vhd
+
+test_bench_files =

libraries/technology/mult/tech_complex_mult.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2009
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, technology_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE work.tech_mult_component_pkg.ALL;
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_stratixiv_mult_lib;
+
+
+ENTITY tech_complex_mult IS
+  GENERIC (
+    g_technology       : NATURAL  := c_tech_select_default;
+    g_variant          : STRING := "IP";
+    g_in_a_w           : POSITIVE;
+    g_in_b_w           : POSITIVE;
+    g_out_p_w          : POSITIVE;          -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
+    g_conjugate_b      : BOOLEAN := FALSE;
+    g_pipeline_input   : NATURAL := 1;      -- 0 or 1
+    g_pipeline_product : NATURAL := 0;      -- 0 or 1
+    g_pipeline_adder   : NATURAL := 1;      -- 0 or 1
+    g_pipeline_output  : NATURAL := 1       -- >= 0
+  );
+  PORT (
+    rst        : IN   STD_LOGIC := '0';
+    clk        : IN   STD_LOGIC;
+    clken      : IN   STD_LOGIC := '1';
+    in_ar      : IN   STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
+    in_ai      : IN   STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
+    in_br      : IN   STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
+    in_bi      : IN   STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
+    result_re  : OUT  STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0);
+    result_im  : OUT  STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0)
+  );
+END tech_complex_mult;
+
+ARCHITECTURE str of tech_complex_mult is 
+
+  -- Force to maximum 18 bit width, because:
+  -- . the ip_stratixiv_complex_mult is generated for 18b inputs and 36b output and then uses 4 real multipliers and no additional registers
+  -- . if one input   > 18b then another IP needs to be regenerated and that will use  8 real multipliers and some extra LUTs and registers
+  -- . if both inputs > 18b then another IP needs to be regenerated and that will use 16 real multipliers and some extra LUTs and registers
+  -- . if the output is set to 18b+18b + 1b =37b to account for the sum then another IP needs to be regenerated and that will use some extra registers
+  -- ==> for inputs <= 18b this ip_stratixiv_complex_mult is appropriate and it can not be made parametrisable to fit also inputs > 18b.
+  CONSTANT c_dsp_dat_w    : NATURAL  := 18;
+  CONSTANT c_dsp_prod_w   : NATURAL  := 2*c_dsp_dat_w;
+  
+  SIGNAL ar        : STD_LOGIC_VECTOR(c_dsp_dat_w-1 DOWNTO 0);
+  SIGNAL ai        : STD_LOGIC_VECTOR(c_dsp_dat_w-1 DOWNTO 0);
+  SIGNAL br        : STD_LOGIC_VECTOR(c_dsp_dat_w-1 DOWNTO 0);
+  SIGNAL bi        : STD_LOGIC_VECTOR(c_dsp_dat_w-1 DOWNTO 0);
+  SIGNAL mult_re   : STD_LOGIC_VECTOR(c_dsp_prod_w-1 DOWNTO 0);
+  SIGNAL mult_im   : STD_LOGIC_VECTOR(c_dsp_prod_w-1 DOWNTO 0);
+
+begin
+
+  gen_ip_stratixiv_ip : IF (g_technology=c_tech_stratixiv AND g_variant="IP") GENERATE
+
+    -- Adapt DSP input widths
+    ar <= RESIZE_SVEC(in_ar, c_dsp_dat_w);
+    ai <= RESIZE_SVEC(in_ai, c_dsp_dat_w);
+    br <= RESIZE_SVEC(in_br, c_dsp_dat_w);
+    bi <= RESIZE_SVEC(in_bi, c_dsp_dat_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_dat_w);
+
+    u0 : ip_stratixiv_complex_mult
+    PORT MAP (
+         aclr        => rst,
+         clock       => clk,
+         dataa_imag  => ai,
+         dataa_real  => ar,
+         datab_imag  => bi,
+         datab_real  => br,
+         ena         => clken,
+         result_imag => mult_im,
+         result_real => mult_re
+         );
+
+    -- Back to true input widths and then resize for output width
+    result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
+    result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
+
+  END GENERATE;
+   
+  gen_ip_stratixiv_rtl : IF (g_technology=c_tech_stratixiv AND g_variant="RTL") GENERATE
+    u0 : ip_stratixiv_complex_mult_rtl
+  GENERIC MAP(
+    g_in_a_w           => g_in_a_w,
+    g_in_b_w           => g_in_b_w,
+    g_out_p_w          => g_out_p_w,
+    g_conjugate_b      => g_conjugate_b,
+    g_pipeline_input   => g_pipeline_input,
+    g_pipeline_product => g_pipeline_product,
+    g_pipeline_adder   => g_pipeline_adder,
+    g_pipeline_output  => g_pipeline_output
+  )
+  PORT MAP(
+    rst        => rst,
+    clk        => clk,
+    clken      => clken,
+    in_ar      => in_ar,
+    in_ai      => in_ai,
+    in_br      => in_br,
+    in_bi      => in_bi,
+    result_re  => result_re,
+    result_im  => result_im
+    );
+  END GENERATE;
+
+end str;
+

libraries/technology/mult/tech_mult.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2009
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, technology_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE work.tech_mult_component_pkg.ALL;
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_stratixiv_mult_lib;
+
+
+ENTITY tech_mult IS
+  GENERIC (
+    g_technology       : NATURAL  := c_tech_select_default;
+    g_variant          : STRING := "IP";
+    g_in_a_w           : POSITIVE := 18;
+    g_in_b_w           : POSITIVE := 18;
+    g_out_p_w          : POSITIVE := 36;      -- c_prod_w = g_in_a_w+g_in_b_w, use smaller g_out_p_w to truncate MSbits, or larger g_out_p_w to extend MSbits
+    g_nof_mult         : POSITIVE := 1;       -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
+    g_pipeline_input   : NATURAL  := 1;        -- 0 or 1
+    g_pipeline_product : NATURAL  := 1;        -- 0 or 1
+    g_pipeline_output  : NATURAL  := 1;        -- >= 0
+    g_representation   : STRING   := "SIGNED"   -- or "UNSIGNED"
+  );
+  PORT (
+    rst        : IN  STD_LOGIC;
+    clk        : IN  STD_LOGIC;
+    clken      : IN  STD_LOGIC := '1';
+    in_a       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
+    in_b       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
+    out_p      : OUT STD_LOGIC_VECTOR(g_nof_mult*g_out_p_w-1 DOWNTO 0)
+  );
+END tech_mult;
+
+ARCHITECTURE str of tech_mult is 
+
+  -- When g_out_p_w < g_in_a_w+g_in_b_w then the LPM_MULT truncates the LSbits of the product. Therefore
+  -- define c_prod_w to be able to let common_mult truncate the LSBits of the product.
+  CONSTANT c_prod_w : NATURAL := g_in_a_w + g_in_b_w;
+
+  SIGNAL prod  : STD_LOGIC_VECTOR(g_nof_mult*c_prod_w-1 DOWNTO 0);
+
+begin
+
+  gen_ip_stratixiv_ip : IF (g_technology=c_tech_stratixiv AND g_variant="IP") GENERATE
+    u0 : ip_stratixiv_mult
+  GENERIC MAP(
+    g_in_a_w           => g_in_a_w,
+    g_in_b_w           => g_in_b_w,
+    g_out_p_w          => g_out_p_w,
+    g_nof_mult         => g_nof_mult,
+    g_pipeline_input   => g_pipeline_input,
+    g_pipeline_product => g_pipeline_product,
+    g_pipeline_output  => g_pipeline_output,
+    g_representation   => g_representation
+  )
+  PORT MAP(
+    clk        => clk,
+    clken      => clken,
+    in_a       => in_a,
+    in_b       => in_b,
+    out_p      => prod
+    );
+  END GENERATE;
+   
+  gen_ip_stratixiv_rtl : IF (g_technology=c_tech_stratixiv AND g_variant="RTL") GENERATE
+    u0 : ip_stratixiv_mult_rtl
+  GENERIC MAP(
+    g_in_a_w           => g_in_a_w,
+    g_in_b_w           => g_in_b_w,
+    g_out_p_w          => g_out_p_w,
+    g_nof_mult         => g_nof_mult,
+    g_pipeline_input   => g_pipeline_input,
+    g_pipeline_product => g_pipeline_product,
+    g_pipeline_output  => g_pipeline_output,
+    g_representation   => g_representation
+  )
+  PORT MAP(
+    rst        => rst,
+    clk        => clk,
+    clken      => clken,
+    in_a       => in_a,
+    in_b       => in_b,
+    out_p      => prod
+    );
+  END GENERATE;
+
+  gen_trunk : FOR I IN 0 TO g_nof_mult-1 GENERATE
+  -- Truncate MSbits, also for signed (common_pkg.vhd for explanation of RESIZE_SVEC)
+    out_p((I+1)*g_out_p_w-1 DOWNTO I*g_out_p_w) <= RESIZE_SVEC(prod((I+1)*c_prod_w-1 DOWNTO I*c_prod_w), g_out_p_w) WHEN g_representation="SIGNED" ELSE
+                                                  RESIZE_UVEC(prod((I+1)*c_prod_w-1 DOWNTO I*c_prod_w), g_out_p_w);
+  END GENERATE;
+
+end str;
+

libraries/technology/mult/tech_mult_component_pkg.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: IP components declarations for various devices that get wrapped by the tech components
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+PACKAGE tech_mult_component_pkg IS
+
+  -----------------------------------------------------------------------------
+  -- complex mult stratixiv ip component
+  -----------------------------------------------------------------------------
+  
+  COMPONENT ip_stratixiv_complex_mult IS
+  PORT
+  (
+    aclr          : IN STD_LOGIC ;
+    clock         : IN STD_LOGIC ;
+    dataa_imag    : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+    dataa_real    : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+    datab_imag    : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+    datab_real    : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+    ena           : IN STD_LOGIC ;
+    result_imag   : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
+    result_real   : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
+  );
+  END COMPONENT;
+  -----------------------------------------------------------------------------
+  -- complex mult stratixiv rtl component
+  -----------------------------------------------------------------------------
+  
+  COMPONENT ip_stratixiv_complex_mult_rtl IS
+  GENERIC (
+    g_in_a_w           : POSITIVE := 18;
+    g_in_b_w           : POSITIVE := 18;
+    g_out_p_w          : POSITIVE := 36;
+    g_conjugate_b      : BOOLEAN := FALSE;
+    g_pipeline_input   : NATURAL := 1;      -- 0 or 1
+    g_pipeline_product : NATURAL := 0;      -- 0 or 1
+    g_pipeline_adder   : NATURAL := 1;      -- 0 or 1
+    g_pipeline_output  : NATURAL := 1       -- >= 0
+  );
+  PORT (
+    rst        : IN   STD_LOGIC := '0';
+    clk        : IN   STD_LOGIC;
+    clken      : IN   STD_LOGIC := '1';
+    in_ar      : IN   STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
+    in_ai      : IN   STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
+    in_br      : IN   STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
+    in_bi      : IN   STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
+    result_re  : OUT  STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0);
+    result_im  : OUT  STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0)
+  );
+  END COMPONENT;
+
+  -----------------------------------------------------------------------------
+  -- mult stratixiv ip component
+  -----------------------------------------------------------------------------
+
+  COMPONENT ip_stratixiv_mult IS 
+  GENERIC (
+    g_in_a_w           : POSITIVE := 18;
+    g_in_b_w           : POSITIVE := 18;
+    g_out_p_w          : POSITIVE := 36;      -- c_prod_w = g_in_a_w+g_in_b_w, use smaller g_out_p_w to truncate MSbits, or larger g_out_p_w to extend MSbits
+    g_nof_mult         : POSITIVE := 1;       -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
+    g_pipeline_input   : NATURAL  := 1;        -- 0 or 1
+    g_pipeline_product : NATURAL  := 1;        -- 0 or 1
+    g_pipeline_output  : NATURAL  := 1;        -- >= 0
+    g_representation   : STRING   := "SIGNED"   -- or "UNSIGNED"
+  );
+  PORT (
+    clk        : IN  STD_LOGIC;
+    clken      : IN  STD_LOGIC := '1';
+    in_a       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
+    in_b       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
+    out_p      : OUT STD_LOGIC_VECTOR(g_nof_mult*(g_in_a_w+g_in_b_w)-1 DOWNTO 0)
+  );
+ END COMPONENT;
+
+ COMPONENT ip_stratixiv_mult_rtl IS 
+  GENERIC (
+    g_in_a_w           : POSITIVE := 18;
+    g_in_b_w           : POSITIVE := 18;
+    g_out_p_w          : POSITIVE := 36;      -- c_prod_w = g_in_a_w+g_in_b_w, use smaller g_out_p_w to truncate MSbits, or larger g_out_p_w to extend MSbits
+    g_nof_mult         : POSITIVE := 1;       -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
+    g_pipeline_input   : NATURAL  := 1;        -- 0 or 1
+    g_pipeline_product : NATURAL  := 1;        -- 0 or 1
+    g_pipeline_output  : NATURAL  := 1;        -- >= 0
+    g_representation   : STRING   := "SIGNED"   -- or "UNSIGNED"
+  );
+  PORT (
+    rst        : IN  STD_LOGIC;
+    clk        : IN  STD_LOGIC;
+    clken      : IN  STD_LOGIC := '1';
+    in_a       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
+    in_b       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
+    out_p      : OUT STD_LOGIC_VECTOR(g_nof_mult*(g_in_a_w+g_in_b_w)-1 DOWNTO 0)
+  );
+ END COMPONENT;
+
+  -----------------------------------------------------------------------------
+  -- arria10 ip component
+  -----------------------------------------------------------------------------
+ 
+  -----------------------------------------------------------------------------
+  -- arria10 rtl component
+  -----------------------------------------------------------------------------
+  
+END tech_mult_component_pkg;

libraries/technology/mult/tech_mult_pkg.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+PACKAGE tech_mult_pkg IS  
+
+  TYPE t_c_tech_mult_variant IS RECORD
+    -- PHY variant within a technology
+    name  : STRING(1 TO 3);  -- = "RTL" or " IP"
+    ip    : BOOLEAN;  -- = TRUE  TRUE = Megawizard IP, FALSE = RTL implemenation
+  END RECORD;
+
+  --                                                                      name    ip
+  CONSTANT c_tech_mult_stratixiv_rtl                  : t_c_tech_mult_variant := ("RTL",  FALSE);
+  CONSTANT c_tech_mult_stratixiv_ip                   : t_c_tech_mult_variant := (" IP",  TRUE);
+  CONSTANT c_tech_mult_arria10_rtl                    : t_c_tech_mult_variant := ("RTL",  FALSE);
+  CONSTANT c_tech_mult_arria10_ip                     : t_c_tech_mult_variant := (" IP",  TRUE);
+
+END tech_mult_pkg;
\ No newline at end of file