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RTSD
HDL
Commits
de1680ae
Commit
de1680ae
authored
3 years ago
by
Eric Kooistra
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Default use round half to even, to have unbiased power values.
parent
1649713a
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!234
Use g_round_even = false in tb, because golden results use round half away...
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libraries/base/common/src/vhdl/common_requantize.vhd
+1
-1
1 addition, 1 deletion
libraries/base/common/src/vhdl/common_requantize.vhd
libraries/base/dp/src/vhdl/dp_requantize.vhd
+1
-1
1 addition, 1 deletion
libraries/base/dp/src/vhdl/dp_requantize.vhd
with
2 additions
and
2 deletions
libraries/base/common/src/vhdl/common_requantize.vhd
+
1
−
1
View file @
de1680ae
...
@@ -59,7 +59,7 @@ ENTITY common_requantize IS
...
@@ -59,7 +59,7 @@ ENTITY common_requantize IS
-- when 0 then no effect
-- when 0 then no effect
g_lsb_round
:
BOOLEAN
:
=
TRUE
;
-- when TRUE round else truncate the input LSbits
g_lsb_round
:
BOOLEAN
:
=
TRUE
;
-- when TRUE round else truncate the input LSbits
g_lsb_round_clip
:
BOOLEAN
:
=
FALSE
;
-- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
g_lsb_round_clip
:
BOOLEAN
:
=
FALSE
;
-- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
g_lsb_round_even
:
BOOLEAN
:
=
FALS
E
;
-- when TRUE round to even, else round away from zero
g_lsb_round_even
:
BOOLEAN
:
=
TRU
E
;
-- when TRUE round
half
to even, else round
half
away from zero
g_msb_clip
:
BOOLEAN
:
=
TRUE
;
-- when TRUE CLIP else WRAP the input MSbits
g_msb_clip
:
BOOLEAN
:
=
TRUE
;
-- when TRUE CLIP else WRAP the input MSbits
g_msb_clip_symmetric
:
BOOLEAN
:
=
FALSE
;
-- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
g_msb_clip_symmetric
:
BOOLEAN
:
=
FALSE
;
-- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
-- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
-- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
...
...
This diff is collapsed.
Click to expand it.
libraries/base/dp/src/vhdl/dp_requantize.vhd
+
1
−
1
View file @
de1680ae
...
@@ -41,7 +41,7 @@ ENTITY dp_requantize IS
...
@@ -41,7 +41,7 @@ ENTITY dp_requantize IS
-- when 0 then no effect
-- when 0 then no effect
g_lsb_round
:
BOOLEAN
:
=
TRUE
;
-- when TRUE round else truncate the input LSbits
g_lsb_round
:
BOOLEAN
:
=
TRUE
;
-- when TRUE round else truncate the input LSbits
g_lsb_round_clip
:
BOOLEAN
:
=
FALSE
;
-- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
g_lsb_round_clip
:
BOOLEAN
:
=
FALSE
;
-- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
g_lsb_round_even
:
BOOLEAN
:
=
FALS
E
;
-- when TRUE round to even, else round away from zero
g_lsb_round_even
:
BOOLEAN
:
=
TRU
E
;
-- when TRUE round
half
to even, else round
half
away from zero
g_msb_clip
:
BOOLEAN
:
=
TRUE
;
-- when TRUE CLIP else WRAP the input MSbits
g_msb_clip
:
BOOLEAN
:
=
TRUE
;
-- when TRUE CLIP else WRAP the input MSbits
g_msb_clip_symmetric
:
BOOLEAN
:
=
FALSE
;
-- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
g_msb_clip_symmetric
:
BOOLEAN
:
=
FALSE
;
-- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
-- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
-- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
...
...
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