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Commit ddff7dbc authored by Daniel van der Schuur's avatar Daniel van der Schuur
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-Connected dp_offload_tx's MM header data bus.

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applications/apertif/designs/apertif_unb1_correlator/quartus/qsys_apertif_unb1_correlator.qsys
+ 152
− 61
View file @ ddff7dbc
......@@ -24,7 +24,7 @@
{
datum baseAddress
{
value = "400";
value = "1680";
type = "long";
}
}
......@@ -133,84 +133,97 @@
type = "boolean";
}
}
element rom_system_info.mem
element reg_unb_sens.mem
{
datum _lockedAddress
datum baseAddress
{
value = "1";
type = "boolean";
value = "1600";
type = "long";
}
}
element reg_dp_offload_tx_hdr_dat.mem
{
datum baseAddress
{
value = "4096";
value = "256";
type = "long";
}
}
element reg_mdio_2.mem
element reg_dp_offload_rx_hdr_dat.mem
{
datum baseAddress
{
value = "256";
value = "512";
type = "long";
}
}
element reg_diag_data_buf.mem
element reg_bsn_monitor.mem
{
datum baseAddress
{
value = "408";
value = "1024";
type = "long";
}
}
element pio_pps.mem
element reg_wdi.mem
{
datum _lockedAddress
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "416";
value = "12288";
type = "long";
}
}
element reg_tr_xaui.mem
element reg_mdio_1.mem
{
datum baseAddress
{
value = "16384";
value = "224";
type = "long";
}
}
element reg_bsn_monitor.mem
element reg_tr_10GbE.mem
{
datum _tags
{
value = "";
type = "String";
}
datum baseAddress
{
value = "1024";
value = "262144";
type = "long";
}
}
element reg_dp_offload_rx_hdr_dat.mem
element reg_diag_data_buf.mem
{
datum baseAddress
{
value = "512";
value = "1688";
type = "long";
}
}
element reg_mdio_1.mem
element reg_mdio_2.mem
{
datum baseAddress
{
value = "224";
value = "1536";
type = "long";
}
}
element reg_unb_sens.mem
element reg_mdio_0.mem
{
datum baseAddress
{
value = "320";
value = "1568";
type = "long";
}
}
element reg_wdi.mem
element rom_system_info.mem
{
datum _lockedAddress
{
......@@ -219,7 +232,7 @@
}
datum baseAddress
{
value = "12288";
value = "4096";
type = "long";
}
}
......@@ -236,40 +249,35 @@
type = "long";
}
}
element ram_diag_data_buf.mem
element reg_tr_xaui.mem
{
datum baseAddress
{
value = "8192";
value = "16384";
type = "long";
}
}
element reg_tr_10GbE.mem
{
datum _tags
element ram_fil_coefs.mem
{
value = "";
type = "String";
}
datum baseAddress
{
value = "262144";
value = "14336";
type = "long";
}
}
element ram_fil_coefs.mem
element pio_pps.mem
{
datum baseAddress
{
value = "14336";
value = "1696";
type = "long";
}
}
element reg_mdio_0.mem
element ram_diag_data_buf.mem
{
datum baseAddress
{
value = "288";
value = "8192";
type = "long";
}
}
......@@ -376,7 +384,7 @@
{
datum baseAddress
{
value = "384";
value = "1664";
type = "long";
}
}
......@@ -422,6 +430,14 @@
type = "String";
}
}
element reg_bsn_monitor.read
{
datum _tags
{
value = "";
type = "String";
}
}
element reg_bsn_monitor
{
datum _sortIndex
......@@ -456,6 +472,14 @@
type = "boolean";
}
}
element reg_dp_offload_tx_hdr_dat
{
datum _sortIndex
{
value = "25";
type = "int";
}
}
element reg_mdio_0
{
datum _sortIndex
......@@ -550,19 +574,27 @@
type = "boolean";
}
}
element timer_0.s1
element pio_debug_wave.s1
{
datum baseAddress
{
value = "192";
value = "1632";
type = "long";
}
}
element pio_debug_wave.s1
element pio_wdi.s1
{
datum baseAddress
{
value = "1648";
type = "long";
}
}
element timer_0.s1
{
datum baseAddress
{
value = "352";
value = "192";
type = "long";
}
}
......@@ -579,14 +611,6 @@
type = "long";
}
}
element pio_wdi.s1
{
datum baseAddress
{
value = "368";
type = "long";
}
}
element reg_wdi.system_reset
{
datum _tags
......@@ -639,7 +663,7 @@
<parameter name="projectName">apertif_unb1_correlator.qpf</parameter>
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="1" />
<parameter name="timeStamp" value="1426683809467" />
<parameter name="timeStamp" value="1427808389602" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="mm_clk" internal="export_mm.out_clk" type="clock" dir="start">
......@@ -1289,6 +1313,41 @@
internal="clk_input.clk_in_reset"
type="reset"
dir="end" />
<interface
name="reg_dp_offload_tx_hdr_dat_reset"
internal="reg_dp_offload_tx_hdr_dat.reset"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_hdr_dat_clk"
internal="reg_dp_offload_tx_hdr_dat.clk"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_hdr_dat_address"
internal="reg_dp_offload_tx_hdr_dat.address"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_hdr_dat_write"
internal="reg_dp_offload_tx_hdr_dat.write"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_hdr_dat_writedata"
internal="reg_dp_offload_tx_hdr_dat.writedata"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_hdr_dat_read"
internal="reg_dp_offload_tx_hdr_dat.read"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_hdr_dat_readdata"
internal="reg_dp_offload_tx_hdr_dat.readdata"
type="conduit"
dir="end" />
<module
kind="altera_avalon_onchip_memory2"
version="11.1"
......@@ -1465,7 +1524,7 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x8000' end='0x8800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_mdio_1.mem' start='0xE0' end='0x100' /><slave name='reg_mdio_2.mem' start='0x100' end='0x120' /><slave name='reg_mdio_0.mem' start='0x120' end='0x140' /><slave name='reg_unb_sens.mem' start='0x140' end='0x160' /><slave name='pio_debug_wave.s1' start='0x160' end='0x170' /><slave name='pio_wdi.s1' start='0x170' end='0x180' /><slave name='altpll_0.pll_slave' start='0x180' end='0x190' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x190' end='0x198' /><slave name='reg_diag_data_buf.mem' start='0x198' end='0x1A0' /><slave name='pio_pps.mem' start='0x1A0' end='0x1A8' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x200' end='0x400' /><slave name='reg_bsn_monitor.mem' start='0x400' end='0x600' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='ram_diag_data_buf.mem' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='ram_fil_coefs.mem' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_tse' start='0x6000' end='0x7000' /><slave name='avs_eth_0.mms_ram' start='0x7000' end='0x8000' /><slave name='cpu_0.jtag_debug_module' start='0x8000' end='0x8800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /></address-map>]]></parameter>
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_mdio_1.mem' start='0xE0' end='0x100' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x200' end='0x400' /><slave name='reg_bsn_monitor.mem' start='0x400' end='0x600' /><slave name='reg_mdio_2.mem' start='0x600' end='0x620' /><slave name='reg_mdio_0.mem' start='0x620' end='0x640' /><slave name='reg_unb_sens.mem' start='0x640' end='0x660' /><slave name='pio_debug_wave.s1' start='0x660' end='0x670' /><slave name='pio_wdi.s1' start='0x670' end='0x680' /><slave name='altpll_0.pll_slave' start='0x680' end='0x690' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x690' end='0x698' /><slave name='reg_diag_data_buf.mem' start='0x698' end='0x6A0' /><slave name='pio_pps.mem' start='0x6A0' end='0x6A8' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='ram_diag_data_buf.mem' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='ram_fil_coefs.mem' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_tse' start='0x6000' end='0x7000' /><slave name='avs_eth_0.mms_ram' start='0x7000' end='0x8000' /><slave name='cpu_0.jtag_debug_module' start='0x8000' end='0x8800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /></address-map>]]></parameter>
<parameter name="clockFrequency" value="50000000" />
<parameter name="deviceFamilyName" value="Stratix IV" />
<parameter name="internalIrqMaskSystemInfo" value="7" />
......@@ -1760,6 +1819,15 @@ q]]></parameter>
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
<module
kind="avs_common_mm"
version="1.0"
enabled="1"
name="reg_dp_offload_tx_hdr_dat">
<parameter name="g_adr_w" value="6" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
</module>
<connection
kind="avalon"
version="11.1"
......@@ -1798,7 +1866,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0190" />
<parameter name="baseAddress" value="0x0690" />
</connection>
<connection
kind="interrupt"
......@@ -1813,7 +1881,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="pio_debug_wave.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0160" />
<parameter name="baseAddress" value="0x0660" />
</connection>
<connection
kind="avalon"
......@@ -1821,7 +1889,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="pio_wdi.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0170" />
<parameter name="baseAddress" value="0x0670" />
</connection>
<connection
kind="avalon"
......@@ -1888,7 +1956,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_diag_data_buf.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0198" />
<parameter name="baseAddress" value="0x0698" />
</connection>
<connection
kind="reset"
......@@ -1932,7 +2000,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_mdio_2.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0100" />
<parameter name="baseAddress" value="0x0600" />
</connection>
<connection
kind="reset"
......@@ -1953,7 +2021,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_mdio_0.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0120" />
<parameter name="baseAddress" value="0x0620" />
</connection>
<connection
kind="avalon"
......@@ -1990,7 +2058,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_unb_sens.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0140" />
<parameter name="baseAddress" value="0x0640" />
</connection>
<connection
kind="reset"
......@@ -2016,7 +2084,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x01a0" />
<parameter name="baseAddress" value="0x06a0" />
</connection>
<connection
kind="reset"
......@@ -2057,7 +2125,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="altpll_0.pll_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0180" />
<parameter name="baseAddress" value="0x0680" />
</connection>
<connection
kind="reset"
......@@ -2315,4 +2383,27 @@ q]]></parameter>
version="11.1"
start="clk_input.clk_reset"
end="avs_eth_0.mm_reset" />
<connection
kind="clock"
version="11.1"
start="altpll_0.c0"
end="reg_dp_offload_tx_hdr_dat.system" />
<connection
kind="reset"
version="11.1"
start="clk_input.clk_reset"
end="reg_dp_offload_tx_hdr_dat.system_reset" />
<connection
kind="reset"
version="11.1"
start="cpu_0.jtag_debug_module_reset"
end="reg_dp_offload_tx_hdr_dat.system_reset" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
end="reg_dp_offload_tx_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0100" />
</connection>
</system>
applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd
+ 10
− 2
View file @ ddff7dbc
......@@ -260,6 +260,10 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
SIGNAL reg_diag_data_buf_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_miso : t_mem_miso;
-- MM 1GbE visibility offload TX
SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
-- Interface: 10GbE
SIGNAL xaui_tx_arr : t_xaui_arr(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL xaui_rx_arr : t_xaui_arr(c_nof_10GbE_streams-1 DOWNTO 0);
......@@ -821,8 +825,8 @@ BEGIN
dp_rst => dp_rst,
dp_clk => dp_clk,
-- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi, FIXME - connect to MMM
-- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
snk_in => apertif_unb1_correlator_vis_offload_snk_in,
snk_out => apertif_unb1_correlator_vis_offload_snk_out,
......@@ -1036,6 +1040,10 @@ BEGIN
ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
ram_diag_data_buf_miso => ram_diag_data_buf_miso,
-- 1GbE visibility offload TX
reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-- Filter coefficients
ram_fil_coefs_mosi => ram_fil_coefs_mosi,
ram_fil_coefs_miso => ram_fil_coefs_miso,
......
applications/apertif/designs/apertif_unb1_correlator/src/vhdl/mmm_apertif_unb1_correlator.vhd
+ 25
− 0
View file @ ddff7dbc
......@@ -102,6 +102,10 @@ ENTITY mmm_apertif_unb1_correlator IS
ram_fil_coefs_mosi : OUT t_mem_mosi;
ram_fil_coefs_miso : IN t_mem_miso;
-- 1GbE visibility Offload TX
reg_dp_offload_tx_hdr_dat_mosi : OUT t_mem_mosi;
reg_dp_offload_tx_hdr_dat_miso : IN t_mem_miso;
-- eth1g
eth1g_tse_clk : OUT STD_LOGIC;
eth1g_mm_rst : OUT STD_LOGIC;
......@@ -136,6 +140,11 @@ ARCHITECTURE str OF mmm_apertif_unb1_correlator IS
-- BSN monitors
CONSTANT c_reg_rsp_bsn_monitor_adr_w : NATURAL := ceil_log2((c_nof_inputs+1+1)* pow2(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
-- 1GbE Visibility offload TX
CONSTANT c_nof_header_fields : NATURAL := 34+3; -- 34 fields but 3 fields (MACs and timestamp) occupy an extra 32b register word
CONSTANT c_reg_dp_offload_tx_hdr_dat_nof_words : NATURAL := c_nof_header_fields;
CONSTANT c_reg_dp_offload_tx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_dat_nof_words);
-- ( 64 * 8 / 1 )
CONSTANT c_ram_fil_coefs_addr_w : natural := ceil_log2(g_wpfb.nof_points * g_wpfb.nof_taps / g_wpfb.wb_factor);
......@@ -254,6 +263,13 @@ ARCHITECTURE str OF mmm_apertif_unb1_correlator IS
eth1g_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
eth1g_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
eth1g_irq_export : in std_logic := 'X'; -- export
reg_dp_offload_tx_hdr_dat_reset_export : out std_logic; -- export
reg_dp_offload_tx_hdr_dat_clk_export : out std_logic; -- export
reg_dp_offload_tx_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
reg_dp_offload_tx_hdr_dat_write_export : out std_logic; -- export
reg_dp_offload_tx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dp_offload_tx_hdr_dat_read_export : out std_logic; -- export
reg_dp_offload_tx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_unb_sens_reset_export : out std_logic; -- export
reg_unb_sens_clk_export : out std_logic; -- export
reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
......@@ -540,6 +556,15 @@ BEGIN
reg_bsn_monitor_write_export => reg_bsn_monitor_mosi.wr,
reg_bsn_monitor_writedata_export => reg_bsn_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_dp_offload_tx_hdr_dat
reg_dp_offload_tx_hdr_dat_address_export => reg_dp_offload_tx_hdr_dat_mosi.address(c_reg_dp_offload_tx_hdr_dat_adr_w-1 DOWNTO 0),
reg_dp_offload_tx_hdr_dat_clk_export => OPEN,
reg_dp_offload_tx_hdr_dat_read_export => reg_dp_offload_tx_hdr_dat_mosi.rd,
reg_dp_offload_tx_hdr_dat_readdata_export => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
reg_dp_offload_tx_hdr_dat_reset_export => OPEN,
reg_dp_offload_tx_hdr_dat_write_export => reg_dp_offload_tx_hdr_dat_mosi.wr,
reg_dp_offload_tx_hdr_dat_writedata_export => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_tr_xaui
reg_tr_xaui_clk_export => OPEN,
reg_tr_xaui_reset_export => OPEN,
......
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