Moved non-generic checking for sync from dp_stream_pkg function to

st_histogram. Test benches still pass OK.

libraries/base/dp/src/vhdl/dp_stream_pkg.vhd

@@ -1528,13 +1528,11 @@ PACKAGE BODY dp_stream_pkg IS
     VARIABLE result : BOOLEAN;
   BEGIN
     result := FALSE;
-    IF snk_in_a.sync = '0' THEN -- Don't compare across sync periods
     IF snk_in_a.valid='1' AND snk_in_b.valid='1' THEN
       IF snk_in_a.data(data_w-1 DOWNTO 0) = snk_in_b.data(data_w-1 DOWNTO 0) THEN
         result := TRUE;
       END IF;
     END IF;
-    END IF;
     RETURN result;
   END;
 

libraries/dsp/st/src/vhdl/st_histogram.vhd

@@ -96,7 +96,6 @@ LIBRARY IEEE, common_lib, mm_lib, technology_lib, dp_lib;
 USE IEEE.std_logic_1164.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
-USE common_lib.common_str_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
@@ -238,19 +237,15 @@ BEGIN
   -- . With a RAM read->write latency of 3 cycles (c_ram_rd_wr_latency), we need 
   --   a shift register of 4 words (0,1,2,3) deep to prevent simultaneous 
   --   read/writes on the RAM.
-  --   . Element 3 is only and output register
+  --   . Element 3 is only an output register, elements 0,1,2 are compared for
+  --     matching data.
   -- . A sequence of duplicate data could cross a sync period:
-  --   . We need to stop&restart counting duplicates on a sync, don't count
-  --     across sync periods to ensure exactly correct bin values in each sync 
-  --     interval
+  --   . Don't count across sync periods to ensure exactly correct bin values
+  --     in each sync interval.
   --   . We can still get a read on cycle n and a write on cycle n+2 on the 
   --     same address, but that does not matter as the read,write will be on
   --     different RAM blocks (1 RAM block per sync period).
-  --     . snk_in_reg_arr(0).sync='1' : Don't compare with older snk_in_reg_arr(1)
-  --       and (2)
-  --     . snk_in_reg_arr(1).sync='1' : Don't compare with older (2)
-  --     . snk_in_reg_arr(2).sync='1' : OK to compare with both (1) and (0)
-  -- . Input : snk_in
+  -- . Input : snk_in, snk_in_data
   -- . Output: snk_in_reg
   -------------------------------------------------------------------------------
   p_nxt_snk_in_reg_arr: PROCESS(snk_in, snk_in_data, snk_in_reg_arr) IS
@@ -271,24 +266,23 @@ BEGIN
       nxt_snk_in_reg_arr(0).channel <= TO_DP_CHANNEL(1);
 
       -- Overwrite channel field (=count) when duplicate data is found
-      IF func_dp_data_match(snk_in_reg_arr(0), snk_in_reg_arr(1), snk_in_reg_arr(2), g_data_w) THEN
+      -- . Check all possible matches apart from 0==1: simply wait until 0==1 shifts to 1==2.
+      IF func_dp_data_match(snk_in_reg_arr(0), snk_in_reg_arr(1), snk_in_reg_arr(2), g_data_w) AND (snk_in_reg_arr(0).sync='0' AND snk_in_reg_arr(1).sync='0') THEN
           nxt_snk_in_reg_arr(1).valid   <= '0';
           nxt_snk_in_reg_arr(1).channel <= TO_DP_CHANNEL(0);
           nxt_snk_in_reg_arr(2).valid   <= '0'; 
           nxt_snk_in_reg_arr(2).channel <= TO_DP_CHANNEL(0);
           nxt_snk_in_reg_arr(3).channel <= TO_DP_CHANNEL(3); -- 0,1,2 match: put count=3 here
-      ELSIF func_dp_data_match(snk_in_reg_arr(1), snk_in_reg_arr(2), g_data_w) THEN
+      ELSIF func_dp_data_match(snk_in_reg_arr(1), snk_in_reg_arr(2), g_data_w) AND snk_in_reg_arr(1).sync='0' THEN
           nxt_snk_in_reg_arr(2).valid   <= '0';
           nxt_snk_in_reg_arr(2).channel <= TO_DP_CHANNEL(0);
           nxt_snk_in_reg_arr(3).channel <= TO_DP_CHANNEL(2); -- 1,2 match: put count=2 here
-      ELSIF func_dp_data_match(snk_in_reg_arr(0), snk_in_reg_arr(2), g_data_w) THEN
-        IF snk_in_reg_arr(1).sync='0' THEN
+      ELSIF func_dp_data_match(snk_in_reg_arr(0), snk_in_reg_arr(2), g_data_w) AND (snk_in_reg_arr(0).sync='0' AND snk_in_reg_arr(1).sync='0') THEN
           nxt_snk_in_reg_arr(1).valid   <= '0';
           nxt_snk_in_reg_arr(1).channel <= TO_DP_CHANNEL(0);
           nxt_snk_in_reg_arr(3).channel <= TO_DP_CHANNEL(2); -- 0,2 match: put count=2 here
       END IF;
     END IF;
-    END IF;
   END PROCESS;
 
   snk_in_reg <= snk_in_reg_arr(3);