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Commit dd699b4a authored by Jonathan Hargreaves's avatar Jonathan Hargreaves
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Correct tab weights address width

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applications/arts/designs/arts_unb1_sc4/quartus/qsys_mm_master.qsys
+ 175
− 97
View file @ dd699b4a
...@@ -85,43 +85,43 @@ ...@@ -85,43 +85,43 @@
type = "boolean"; type = "boolean";
} }
} }
element reg_dp_xonoff_output.mem element reg_mdio_1.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "1752"; value = "1376";
type = "long"; type = "long";
} }
} }
element reg_mdio_2.mem element reg_epcs.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "1344"; value = "1280";
type = "long"; type = "long";
} }
} }
element reg_diag_data_buffer_wpfbout.mem element reg_bf_unit_x_st_sst.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "3072"; value = "1024";
type = "long"; type = "long";
} }
} }
element reg_dp_gain_i.mem element ram_bf_unit_x_st_sst.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "1552"; value = "1632";
type = "long"; type = "long";
} }
} }
element reg_remu.mem element reg_tab_dest_mac.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "1312"; value = "3392";
type = "long"; type = "long";
} }
} }
...@@ -133,117 +133,117 @@ ...@@ -133,117 +133,117 @@
type = "long"; type = "long";
} }
} }
element reg_dp_bsn_align_mesh.mem element reg_tr_10GbE.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "1440"; value = "262144";
type = "long"; type = "long";
} }
} }
element reg_mdio_1.mem element rom_unb_system_info.mem
{
datum _lockedAddress
{ {
value = "1";
type = "boolean";
}
datum baseAddress datum baseAddress
{ {
value = "1376"; value = "4096";
type = "long"; type = "long";
} }
} }
element reg_dp_offload_tx_tab_i_hdr_dat.mem element reg_diag_data_buffer_wpfbin.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "589824"; value = "3584";
type = "long"; type = "long";
} }
} }
element ram_diag_data_buffer_input.mem element reg_bsn_monitor_input.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "540672"; value = "2048";
type = "long"; type = "long";
} }
} }
element reg_dp_xonoff_tab_iquv.mem element reg_dp_xonoff_tab_i.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "1528"; value = "1536";
type = "long"; type = "long";
} }
} }
element pio_system_info.mem element reg_dp_gain_q.mem
{
datum _lockedAddress
{ {
value = "1";
type = "boolean";
}
datum baseAddress datum baseAddress
{ {
value = "0"; value = "1560";
type = "long"; type = "long";
} }
} }
element ram_diag_data_buffer_wpfbin.mem element ram_diag_data_buffer_meshin.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "524288"; value = "557056";
type = "long"; type = "long";
} }
} }
element reg_ppsh.mem element pio_system_info.mem
{ {
datum _lockedAddress
{
value = "1";
type = "boolean";
}
datum baseAddress datum baseAddress
{ {
value = "1512"; value = "0";
type = "long"; type = "long";
} }
} }
element reg_tab_dest_mac.mem element ram_bf_unit_x_bf_weights.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "3360"; value = "128";
type = "long"; type = "long";
} }
} }
element rom_unb_system_info.mem element reg_dp_bsn_align_mesh.mem
{
datum _lockedAddress
{ {
value = "1";
type = "boolean";
}
datum baseAddress datum baseAddress
{ {
value = "4096"; value = "1440";
type = "long"; type = "long";
} }
} }
element reg_diag_data_buffer_wpfbin.mem element reg_ppsh.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "3584"; value = "1512";
type = "long"; type = "long";
} }
} }
element ram_diag_data_buffer_meshin.mem element ram_diag_data_buffer_wpfbin.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "557056"; value = "524288";
type = "long"; type = "long";
} }
} }
element reg_dp_xonoff_tab_i.mem element ram_diag_data_buffer_wpfbout.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "1536"; value = "573440";
type = "long"; type = "long";
} }
} }
...@@ -255,6 +255,14 @@ ...@@ -255,6 +255,14 @@
type = "long"; type = "long";
} }
} }
element reg_dp_xonoff_tab_iquv.mem
{
datum baseAddress
{
value = "1528";
type = "long";
}
}
element reg_dp_bsn_align_input.mem element reg_dp_bsn_align_input.mem
{ {
datum baseAddress datum baseAddress
...@@ -263,59 +271,59 @@ ...@@ -263,59 +271,59 @@
type = "long"; type = "long";
} }
} }
element reg_force_data_input.mem element reg_dp_gain_i.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "1920"; value = "1552";
type = "long"; type = "long";
} }
} }
element reg_dp_xonoff_iab_i.mem element reg_diag_data_buffer_wpfbout.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "1544"; value = "3072";
type = "long"; type = "long";
} }
} }
element reg_tr_10GbE.mem element reg_remu.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "262144"; value = "1312";
type = "long"; type = "long";
} }
} }
element reg_bf_unit_x_st_sst.mem element ram_arts_tab_beamformer.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "1024"; value = "786432";
type = "long"; type = "long";
} }
} }
element ram_bf_unit_x_ss_ss_wide.mem element reg_dp_offload_tx_hdr_dat.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "1344"; value = "256";
type = "long"; type = "long";
} }
} }
element reg_mdio_0.mem element reg_unb_sens.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "1408"; value = "224";
type = "long"; type = "long";
} }
} }
element reg_dp_gain_v.mem element reg_dp_offload_tx_iab_i_hdr_dat.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "1576"; value = "1024";
type = "long"; type = "long";
} }
} }
...@@ -327,43 +335,43 @@ ...@@ -327,43 +335,43 @@
type = "long"; type = "long";
} }
} }
element reg_bsn_monitor_input.mem element reg_dp_offload_tx_tab_i_hdr_dat.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "2048"; value = "589824";
type = "long"; type = "long";
} }
} }
element ram_bf_unit_x_bf_weights.mem element reg_wdi.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "128"; value = "1520";
type = "long"; type = "long";
} }
} }
element reg_dp_offload_tx_hdr_dat.mem element reg_dp_xonoff_output.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "256"; value = "1752";
type = "long"; type = "long";
} }
} }
element reg_tab_dest_ip.mem element reg_mdio_2.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "3328"; value = "1344";
type = "long"; type = "long";
} }
} }
element reg_epcs.mem element reg_mdio_0.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "1280"; value = "1408";
type = "long"; type = "long";
} }
} }
...@@ -375,19 +383,19 @@ ...@@ -375,19 +383,19 @@
type = "long"; type = "long";
} }
} }
element reg_dp_gain_q.mem element ram_bf_unit_x_ss_ss_wide.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "1560"; value = "1344";
type = "long"; type = "long";
} }
} }
element reg_wdi.mem element ram_diag_data_buffer_input.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "1520"; value = "540672";
type = "long"; type = "long";
} }
} }
...@@ -399,43 +407,43 @@ ...@@ -399,43 +407,43 @@
type = "long"; type = "long";
} }
} }
element ram_bf_unit_x_st_sst.mem element reg_dp_xonoff_iab_i.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "1632"; value = "1544";
type = "long"; type = "long";
} }
} }
element reg_dp_offload_tx_iab_i_hdr_dat.mem element reg_force_data_input.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "1024"; value = "1920";
type = "long"; type = "long";
} }
} }
element reg_unb_sens.mem element reg_diag_data_buffer_meshin.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "224"; value = "548864";
type = "long"; type = "long";
} }
} }
element ram_diag_data_buffer_wpfbout.mem element reg_dp_gain_v.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "573440"; value = "1576";
type = "long"; type = "long";
} }
} }
element reg_diag_data_buffer_meshin.mem element reg_tab_dest_ip.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "548864"; value = "3328";
type = "long"; type = "long";
} }
} }
...@@ -515,6 +523,14 @@ ...@@ -515,6 +523,14 @@
type = "boolean"; type = "boolean";
} }
} }
element ram_arts_tab_beamformer
{
datum _sortIndex
{
value = "51";
type = "int";
}
}
element ram_bf_unit_x_bf_weights element ram_bf_unit_x_bf_weights
{ {
datum _sortIndex datum _sortIndex
...@@ -887,6 +903,14 @@ ...@@ -887,6 +903,14 @@
type = "int"; type = "int";
} }
} }
element timer_0.s1
{
datum baseAddress
{
value = "192";
type = "long";
}
}
element onchip_memory2_0.s1 element onchip_memory2_0.s1
{ {
datum _lockedAddress datum _lockedAddress
...@@ -908,14 +932,6 @@ ...@@ -908,14 +932,6 @@
type = "long"; type = "long";
} }
} }
element timer_0.s1
{
datum baseAddress
{
value = "192";
type = "long";
}
}
element timer_0 element timer_0
{ {
datum _sortIndex datum _sortIndex
...@@ -944,7 +960,7 @@ ...@@ -944,7 +960,7 @@
<parameter name="projectName" value="" /> <parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" /> <parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="1" /> <parameter name="systemHash" value="1" />
<parameter name="timeStamp" value="1522765790586" /> <parameter name="timeStamp" value="1524746959487" />
<parameter name="useTestBenchNamingPattern" value="false" /> <parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript> <instanceScript></instanceScript>
<interface <interface
...@@ -2367,13 +2383,48 @@ ...@@ -2367,13 +2383,48 @@
internal="reg_tab_dest_mac.readdata" internal="reg_tab_dest_mac.readdata"
type="conduit" type="conduit"
dir="end" /> dir="end" />
<interface
name="ram_arts_tab_beamformer_reset"
internal="ram_arts_tab_beamformer.reset"
type="conduit"
dir="end" />
<interface
name="ram_arts_tab_beamformer_clk"
internal="ram_arts_tab_beamformer.clk"
type="conduit"
dir="end" />
<interface
name="ram_arts_tab_beamformer_address"
internal="ram_arts_tab_beamformer.address"
type="conduit"
dir="end" />
<interface
name="ram_arts_tab_beamformer_write"
internal="ram_arts_tab_beamformer.write"
type="conduit"
dir="end" />
<interface
name="ram_arts_tab_beamformer_writedata"
internal="ram_arts_tab_beamformer.writedata"
type="conduit"
dir="end" />
<interface
name="ram_arts_tab_beamformer_read"
internal="ram_arts_tab_beamformer.read"
type="conduit"
dir="end" />
<interface
name="ram_arts_tab_beamformer_readdata"
internal="ram_arts_tab_beamformer.readdata"
type="conduit"
dir="end" />
<module <module
kind="altera_avalon_onchip_memory2" kind="altera_avalon_onchip_memory2"
version="11.1" version="11.1"
enabled="1" enabled="1"
name="onchip_memory2_0"> name="onchip_memory2_0">
<parameter name="allowInSystemMemoryContentEditor" value="false" /> <parameter name="allowInSystemMemoryContentEditor" value="false" />
<parameter name="autoInitializationFileName">qsys_mm_master_onchip_memory2_0</parameter> <parameter name="autoInitializationFileName">$${FILENAME}_onchip_memory2_0</parameter>
<parameter name="blockType" value="M144K" /> <parameter name="blockType" value="M144K" />
<parameter name="dataWidth" value="32" /> <parameter name="dataWidth" value="32" />
<parameter name="deviceFamily" value="Stratix IV" /> <parameter name="deviceFamily" value="Stratix IV" />
...@@ -2525,7 +2576,7 @@ q]]></parameter> ...@@ -2525,7 +2576,7 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" /> <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" /> <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x6000' end='0x6800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter> <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x6000' end='0x6800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_tab_iquv_hdr_dat.mem' start='0x200' end='0x300' /><slave name='reg_dp_offload_tx_iab_i_hdr_dat.mem' start='0x400' end='0x500' /><slave name='reg_epcs.mem' start='0x500' end='0x520' /><slave name='reg_remu.mem' start='0x520' end='0x540' /><slave name='reg_mdio_2.mem' start='0x540' end='0x560' /><slave name='reg_mdio_1.mem' start='0x560' end='0x580' /><slave name='reg_mdio_0.mem' start='0x580' end='0x5A0' /><slave name='reg_dp_bsn_align_mesh.mem' start='0x5A0' end='0x5C0' /><slave name='pio_wdi.s1' start='0x5C0' end='0x5D0' /><slave name='reg_dp_bsn_align_input.mem' start='0x5D0' end='0x5E0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x5E0' end='0x5E8' /><slave name='reg_ppsh.mem' start='0x5E8' end='0x5F0' /><slave name='reg_wdi.mem' start='0x5F0' end='0x5F8' /><slave name='reg_dp_xonoff_tab_iquv.mem' start='0x5F8' end='0x600' /><slave name='reg_dp_xonoff_tab_i.mem' start='0x600' end='0x608' /><slave name='reg_dp_xonoff_iab_i.mem' start='0x608' end='0x610' /><slave name='reg_dp_gain_i.mem' start='0x610' end='0x618' /><slave name='reg_dp_gain_q.mem' start='0x618' end='0x620' /><slave name='reg_dp_gain_u.mem' start='0x620' end='0x628' /><slave name='reg_dp_gain_v.mem' start='0x628' end='0x630' /><slave name='reg_force_data_input.mem' start='0x780' end='0x800' /><slave name='reg_bsn_monitor_input.mem' start='0x800' end='0xA00' /><slave name='reg_bsn_monitor_mesh.mem' start='0xA00' end='0xC00' /><slave name='reg_diag_data_buffer_wpfbout.mem' start='0xC00' end='0xC80' /><slave name='reg_tab_dest_ip.mem' start='0xD00' end='0xD20' /><slave name='reg_tab_dest_mac.mem' start='0xD20' end='0xD40' /><slave name='reg_diag_data_buffer_wpfbin.mem' start='0xE00' end='0x1000' /><slave name='rom_unb_system_info.mem' start='0x1000' end='0x2000' /><slave name='reg_tr_xaui.mem' start='0x2000' end='0x4000' /><slave name='avs_eth_0.mms_tse' start='0x4000' end='0x5000' /><slave name='avs_eth_0.mms_ram' start='0x5000' end='0x6000' /><slave name='cpu_0.jtag_debug_module' start='0x6000' end='0x6800' /><slave name='reg_diag_data_buffer_input.mem' start='0x12000' end='0x12100' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /><slave name='ram_diag_data_buffer_wpfbin.mem' start='0x80000' end='0x84000' /><slave name='ram_diag_data_buffer_input.mem' start='0x84000' end='0x86000' /><slave name='reg_diag_data_buffer_meshin.mem' start='0x86000' end='0x86100' /><slave name='ram_diag_data_buffer_meshin.mem' start='0x88000' end='0x8C000' /><slave name='ram_diag_data_buffer_wpfbout.mem' start='0x8C000' end='0x90000' /><slave name='reg_dp_offload_tx_tab_i_hdr_dat.mem' start='0x90000' end='0x90800' /></address-map>]]></parameter> <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_tab_iquv_hdr_dat.mem' start='0x200' end='0x300' /><slave name='reg_dp_offload_tx_iab_i_hdr_dat.mem' start='0x400' end='0x500' /><slave name='reg_epcs.mem' start='0x500' end='0x520' /><slave name='reg_remu.mem' start='0x520' end='0x540' /><slave name='reg_mdio_2.mem' start='0x540' end='0x560' /><slave name='reg_mdio_1.mem' start='0x560' end='0x580' /><slave name='reg_mdio_0.mem' start='0x580' end='0x5A0' /><slave name='reg_dp_bsn_align_mesh.mem' start='0x5A0' end='0x5C0' /><slave name='pio_wdi.s1' start='0x5C0' end='0x5D0' /><slave name='reg_dp_bsn_align_input.mem' start='0x5D0' end='0x5E0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x5E0' end='0x5E8' /><slave name='reg_ppsh.mem' start='0x5E8' end='0x5F0' /><slave name='reg_wdi.mem' start='0x5F0' end='0x5F8' /><slave name='reg_dp_xonoff_tab_iquv.mem' start='0x5F8' end='0x600' /><slave name='reg_dp_xonoff_tab_i.mem' start='0x600' end='0x608' /><slave name='reg_dp_xonoff_iab_i.mem' start='0x608' end='0x610' /><slave name='reg_dp_gain_i.mem' start='0x610' end='0x618' /><slave name='reg_dp_gain_q.mem' start='0x618' end='0x620' /><slave name='reg_dp_gain_u.mem' start='0x620' end='0x628' /><slave name='reg_dp_gain_v.mem' start='0x628' end='0x630' /><slave name='reg_force_data_input.mem' start='0x780' end='0x800' /><slave name='reg_bsn_monitor_input.mem' start='0x800' end='0xA00' /><slave name='reg_bsn_monitor_mesh.mem' start='0xA00' end='0xC00' /><slave name='reg_diag_data_buffer_wpfbout.mem' start='0xC00' end='0xC80' /><slave name='reg_tab_dest_ip.mem' start='0xD00' end='0xD20' /><slave name='reg_tab_dest_mac.mem' start='0xD40' end='0xD80' /><slave name='reg_diag_data_buffer_wpfbin.mem' start='0xE00' end='0x1000' /><slave name='rom_unb_system_info.mem' start='0x1000' end='0x2000' /><slave name='reg_tr_xaui.mem' start='0x2000' end='0x4000' /><slave name='avs_eth_0.mms_tse' start='0x4000' end='0x5000' /><slave name='avs_eth_0.mms_ram' start='0x5000' end='0x6000' /><slave name='cpu_0.jtag_debug_module' start='0x6000' end='0x6800' /><slave name='reg_diag_data_buffer_input.mem' start='0x12000' end='0x12100' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /><slave name='ram_diag_data_buffer_wpfbin.mem' start='0x80000' end='0x84000' /><slave name='ram_diag_data_buffer_input.mem' start='0x84000' end='0x86000' /><slave name='reg_diag_data_buffer_meshin.mem' start='0x86000' end='0x86100' /><slave name='ram_diag_data_buffer_meshin.mem' start='0x88000' end='0x8C000' /><slave name='ram_diag_data_buffer_wpfbout.mem' start='0x8C000' end='0x90000' /><slave name='reg_dp_offload_tx_tab_i_hdr_dat.mem' start='0x90000' end='0x90800' /><slave name='ram_arts_tab_beamformer.mem' start='0xC0000' end='0x100000' /></address-map>]]></parameter>
<parameter name="clockFrequency" value="25000000" /> <parameter name="clockFrequency" value="25000000" />
<parameter name="deviceFamilyName" value="Stratix IV" /> <parameter name="deviceFamilyName" value="Stratix IV" />
<parameter name="internalIrqMaskSystemInfo" value="7" /> <parameter name="internalIrqMaskSystemInfo" value="7" />
...@@ -2885,7 +2936,16 @@ q]]></parameter> ...@@ -2885,7 +2936,16 @@ q]]></parameter>
version="1.0" version="1.0"
enabled="1" enabled="1"
name="reg_tab_dest_mac"> name="reg_tab_dest_mac">
<parameter name="g_adr_w" value="3" /> <parameter name="g_adr_w" value="4" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
<module
kind="avs_common_mm"
version="1.0"
enabled="1"
name="ram_arts_tab_beamformer">
<parameter name="g_adr_w" value="16" />
<parameter name="g_dat_w" value="32" /> <parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" /> <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module> </module>
...@@ -3955,7 +4015,7 @@ q]]></parameter> ...@@ -3955,7 +4015,7 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="reg_tab_dest_mac.mem"> end="reg_tab_dest_mac.mem">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0d20" /> <parameter name="baseAddress" value="0x0d40" />
</connection> </connection>
<connection <connection
kind="clock" kind="clock"
...@@ -3967,4 +4027,22 @@ q]]></parameter> ...@@ -3967,4 +4027,22 @@ q]]></parameter>
version="11.1" version="11.1"
start="clk_input.clk_reset" start="clk_input.clk_reset"
end="reg_tab_dest_mac.system_reset" /> end="reg_tab_dest_mac.system_reset" />
<connection
kind="clock"
version="11.1"
start="clk_input.clk"
end="ram_arts_tab_beamformer.system" />
<connection
kind="reset"
version="11.1"
start="clk_input.clk_reset"
end="ram_arts_tab_beamformer.system_reset" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
end="ram_arts_tab_beamformer.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x000c0000" />
</connection>
</system> </system>
applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_mm_master.vhd
+ 15
− 0
View file @ dd699b4a
...@@ -83,6 +83,8 @@ ENTITY arts_unb1_sc4_mm_master IS ...@@ -83,6 +83,8 @@ ENTITY arts_unb1_sc4_mm_master IS
reg_tr_10gbe_miso : IN t_mem_miso := c_mem_miso_rst; reg_tr_10gbe_miso : IN t_mem_miso := c_mem_miso_rst;
reg_tr_xaui_mosi : OUT t_mem_mosi := c_mem_mosi_rst; reg_tr_xaui_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_tr_xaui_miso : IN t_mem_miso := c_mem_miso_rst; reg_tr_xaui_miso : IN t_mem_miso := c_mem_miso_rst;
ram_arts_tab_beamformer_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
ram_arts_tab_beamformer_miso : IN t_mem_miso := c_mem_miso_rst;
-- ram_bf_unit_ss_ss_wide_mosi_arr : OUT t_mem_mosi_arr(g_nof_polarizations-1 DOWNTO 0) := (OTHERS=>c_mem_mosi_rst); -- ram_bf_unit_ss_ss_wide_mosi_arr : OUT t_mem_mosi_arr(g_nof_polarizations-1 DOWNTO 0) := (OTHERS=>c_mem_mosi_rst);
-- ram_bf_unit_ss_ss_wide_miso_arr : IN t_mem_miso_arr(g_nof_polarizations-1 DOWNTO 0); -- ram_bf_unit_ss_ss_wide_miso_arr : IN t_mem_miso_arr(g_nof_polarizations-1 DOWNTO 0);
-- ram_bf_unit_bf_weights_mosi_arr : OUT t_mem_mosi_arr(g_nof_polarizations-1 DOWNTO 0) := (OTHERS=>c_mem_mosi_rst); -- ram_bf_unit_bf_weights_mosi_arr : OUT t_mem_mosi_arr(g_nof_polarizations-1 DOWNTO 0) := (OTHERS=>c_mem_mosi_rst);
...@@ -281,6 +283,12 @@ ARCHITECTURE str OF arts_unb1_sc4_mm_master IS ...@@ -281,6 +283,12 @@ ARCHITECTURE str OF arts_unb1_sc4_mm_master IS
reg_tr_10GbE_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); reg_tr_10GbE_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
reg_tr_10GbE_waitrequest_export : IN STD_LOGIC; reg_tr_10GbE_waitrequest_export : IN STD_LOGIC;
ram_arts_tab_beamformer_address_export : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
ram_arts_tab_beamformer_read_export : OUT STD_LOGIC;
ram_arts_tab_beamformer_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := (OTHERS => '0');
ram_arts_tab_beamformer_write_export : OUT STD_LOGIC;
ram_arts_tab_beamformer_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
-- ram_bf_unit_x_ss_ss_wide_address_export : OUT STD_LOGIC_VECTOR(4-1 DOWNTO 0); -- ram_bf_unit_x_ss_ss_wide_address_export : OUT STD_LOGIC_VECTOR(4-1 DOWNTO 0);
---- ram_bf_unit_x_ss_ss_wide_clk_export : OUT STD_LOGIC; ---- ram_bf_unit_x_ss_ss_wide_clk_export : OUT STD_LOGIC;
-- ram_bf_unit_x_ss_ss_wide_read_export : OUT STD_LOGIC; -- ram_bf_unit_x_ss_ss_wide_read_export : OUT STD_LOGIC;
...@@ -562,6 +570,7 @@ BEGIN ...@@ -562,6 +570,7 @@ BEGIN
ram_diag_data_buf_input_mosi <= c_mem_mosi_rst; ram_diag_data_buf_input_mosi <= c_mem_mosi_rst;
reg_diag_data_buf_meshin_mosi <= c_mem_mosi_rst; reg_diag_data_buf_meshin_mosi <= c_mem_mosi_rst;
ram_diag_data_buf_meshin_mosi <= c_mem_mosi_rst; ram_diag_data_buf_meshin_mosi <= c_mem_mosi_rst;
ram_arts_tab_beamformer_mosi <= c_mem_mosi_rst;
END GENERATE; END GENERATE;
gen_qsys_mm_master : IF g_sim = FALSE GENERATE gen_qsys_mm_master : IF g_sim = FALSE GENERATE
...@@ -698,6 +707,12 @@ BEGIN ...@@ -698,6 +707,12 @@ BEGIN
reg_tr_xaui_write_export => reg_tr_xaui_mosi.wr, reg_tr_xaui_write_export => reg_tr_xaui_mosi.wr,
reg_tr_xaui_writedata_export => reg_tr_xaui_mosi.wrdata(c_word_w-1 DOWNTO 0), reg_tr_xaui_writedata_export => reg_tr_xaui_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_arts_tab_beamformer_address_export => ram_arts_tab_beamformer_mosi.address(15 DOWNTO 0),
ram_arts_tab_beamformer_read_export => ram_arts_tab_beamformer_mosi.rd,
ram_arts_tab_beamformer_readdata_export => ram_arts_tab_beamformer_miso.rddata(c_word_w-1 DOWNTO 0),
ram_arts_tab_beamformer_write_export => ram_arts_tab_beamformer_mosi.wr,
ram_arts_tab_beamformer_writedata_export => ram_arts_tab_beamformer_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- ram_bf_unit_x_ss_ss_wide_address_export => ram_bf_unit_ss_ss_wide_mosi_arr(0).address(4-1 DOWNTO 0), -- ram_bf_unit_x_ss_ss_wide_address_export => ram_bf_unit_ss_ss_wide_mosi_arr(0).address(4-1 DOWNTO 0),
---- ram_bf_unit_x_ss_ss_wide_clk_export => OPEN, ---- ram_bf_unit_x_ss_ss_wide_clk_export => OPEN,
-- ram_bf_unit_x_ss_ss_wide_read_export => ram_bf_unit_ss_ss_wide_mosi_arr(0).rd, -- ram_bf_unit_x_ss_ss_wide_read_export => ram_bf_unit_ss_ss_wide_mosi_arr(0).rd,
......
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