Added tb_end output for proper ending after all instances in multi tb have finished.

libraries/technology/eth_10g/tb_tb_tech_eth_10g.vhd

@@ -43,9 +43,13 @@ ARCHITECTURE tb OF tb_tb_tech_eth_10g IS
   CONSTANT c_156       : TIME := 6.4 ns;
   CONSTANT c_data_type : NATURAL := c_tb_tech_mac_10g_data_type_symbols;
   
+  CONSTANT c_tb_end_vec : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS=>'1');
+  SIGNAL   tb_end_vec   : STD_LOGIC_VECTOR(1 DOWNTO 0) := c_tb_end_vec;  -- sufficiently long to fit all tb instances
+  
 BEGIN
 
 -- g_technology              : NATURAL := c_tech_select_default;
+-- g_tb_end                  : BOOLEAN := TRUE;   -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
 -- g_sim_level               : NATURAL := 0;     -- 0 = use IP; 1 = use fast serdes model
 -- g_ref_clk_644_period      : TIME := tech_pll_clk_644_period;  -- for 10GBASE-R
 -- g_ref_clk_156_period      : TIME := 6.4 ns;                   -- for XAUI
@@ -54,7 +58,13 @@ BEGIN
 -- g_link_status_check       : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "11";
 -- g_use_serial_rx_in        : BOOLEAN := FALSE 
 
-  u_tech_eth_10g : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, 0, c_644, c_156, c_data_type, TRUE, "11", FALSE);
-  u_sim_eth_10g  : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, 1, c_644, c_156, c_data_type, TRUE, "11", FALSE);
+  u_tech_eth_10g : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, FALSE, 0, c_644, c_156, c_data_type, TRUE, "11", FALSE) PORT MAP (tb_end_vec(0));
+  u_sim_eth_10g  : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, FALSE, 1, c_644, c_156, c_data_type, TRUE, "11", FALSE) PORT MAP (tb_end_vec(1));
   
+  p_tb_end : PROCESS
+  BEGIN
+    WAIT UNTIL tb_end_vec=c_tb_end_vec;
+    REPORT "Multi tb simulation finished." SEVERITY FAILURE;
+    WAIT;
+  END PROCESS;
 END tb;

libraries/technology/eth_10g/tb_tech_eth_10g.vhd

@@ -47,7 +47,8 @@ ENTITY tb_tech_eth_10g IS
   -- Test bench control parameters
   GENERIC (
     g_technology              : NATURAL := c_tech_select_default;
-    g_sim_level               : NATURAL := 0;     -- 0 = use IP; 1 = use fast serdes model
+    g_tb_end                  : BOOLEAN := TRUE;   -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+    g_sim_level               : NATURAL := 1;     -- 0 = use IP; 1 = use fast serdes model
     g_ref_clk_644_period      : TIME := tech_pll_clk_644_period;  -- for 10GBASE-R
     g_ref_clk_156_period      : TIME := 6.4 ns;                   -- for XAUI
     g_data_type               : NATURAL := c_tb_tech_mac_10g_data_type_symbols;
@@ -56,6 +57,7 @@ ENTITY tb_tech_eth_10g IS
     g_use_serial_rx_in        : BOOLEAN := FALSE 
   );
   PORT (
+    tb_end          : OUT STD_LOGIC;
     -- PHY 10gbase_r
     serial_tx_out   : OUT STD_LOGIC;                                       -- 1 lane
     serial_rx_in    : IN  STD_LOGIC := 'X';
@@ -97,7 +99,6 @@ ARCHITECTURE tb OF tb_tech_eth_10g IS
   
   -- Clocks and reset
   SIGNAL rx_end            : STD_LOGIC := '0';
-  SIGNAL tb_end            : STD_LOGIC := '0';
   SIGNAL mm_clk            : STD_LOGIC := '0';  -- memory-mapped bus clock
   SIGNAL mm_rst            : STD_LOGIC;         -- reset synchronous with mm_clk
   
@@ -186,7 +187,7 @@ BEGIN
     g_src_mac       => c_src_mac
   )
   PORT MAP (
-    tb_end    => tb_end,
+    tb_end    => rx_end,
     mm_clk    => mm_clk,
     mm_rst    => mm_rst,
     mm_init   => mm_init,
@@ -379,13 +380,18 @@ BEGIN
   
   p_tb_end : PROCESS  
   BEGIN
+    tb_end <= '0';
     WAIT UNTIL rx_end='1';
     proc_common_wait_some_cycles(tb_tx_clk, 100);
     --proc_common_wait_some_cycles(tb_tx_clk, 10000);  -- uncomment to simulate somewhat longer without tx packet data
     
     -- Stop the simulation
     tb_end <= '1';
-    ASSERT FALSE REPORT "Simulation finished." SEVERITY FAILURE;
+    IF g_tb_end=FALSE THEN
+      REPORT "Tb Simulation finished." SEVERITY NOTE;
+    ELSE
+      REPORT "Tb Simulation finished." SEVERITY FAILURE;
+    END IF;
     WAIT;
   END PROCESS;