Add to_sl(), to_int(), c_tree_delay_len.

libraries/base/common/src/vhdl/common_pkg.vhd

@@ -86,6 +86,7 @@ package common_pkg is
   constant c_eps                  : real := 1.0e-20;  -- add small epsilon value to avoid 1/0 and log(0), 1e-20 < 1/2**64
 
   -- FF, block RAM, FIFO
+  constant c_tree_delay_len       : natural := 10;  -- reset clock tree pipelining to facilitate FF duplication by synthesis tool
   constant c_meta_delay_len       : natural := 3;  -- default nof flipflops (FF) in meta stability recovery delay line (e.g. for clock domain crossing)
   constant c_meta_fifo_depth      : natural := 16;  -- default use 16 word deep FIFO to cross clock domain, typically > 2*c_meta_delay_len or >~ 8 is enough
 
@@ -215,6 +216,8 @@ package common_pkg is
   function sl( n: in std_logic_vector) return std_logic;  -- 1 element standard logic vector to standard logic
 
   function to_sl(  n: in boolean)   return std_logic;  -- if TRUE     then return '1'   else '0'
+  function to_sl(  n: in integer)   return std_logic;  -- if 0        then return '0'   else '1'
+  function to_int( n: in std_logic) return integer;  -- if '1' or 'H' then return '1'   else '0'
   function to_bool(n: in std_logic) return boolean;  -- if '1' or 'H' then return TRUE  else FALSE
   function to_bool(n: in integer)   return boolean;  -- if  0         then return FALSE else TRUE
 
@@ -777,6 +780,24 @@ package body common_pkg is
     end if;
   end;
 
+  function to_sl(n: in integer) return std_logic is
+  begin
+    if n = 0 then
+      return '0';
+    else
+      return '1';
+    end if;
+  end;
+
+  function to_int(n: in std_logic) return integer is
+  begin
+    if n = '1' or n = 'H' then
+      return 1;
+    else
+      return 0;
+    end if;
+  end;
+
   function to_bool(n: in std_logic) return boolean is
   begin
     return n = '1' or n = 'H';